LM27403SQ from Texas Instruments, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SS/TRACK	bidirectional	Soft-start or tracking input: a capacitor to GND sets the startup rate, a 3-µA source charges it until the reference reaches 0.6 V, and it can be driven externally from 0 V to VDD for tracking.
2	RS	input	Negative remote sense input that removes the ground drop between GND and the local load ground, with RS limited to -0.1 V to 0.1 V and tied to GND at the IC if unused.
3	FB	input	Voltage-mode error amplifier inverting input that sets the output voltage, held at 0.6 V ±1% in closed-loop regulation.
4	COMP	output	Error amplifier output that is connected to FB through a compensation network to ensure loop stability.
5	FADJ	input	Frequency adjust input whose connected resistor to GND sets the switching frequency, programmable from 200 kHz to 1.2 MHz.
6	SYNC	input	Synchronization input for PLL locking to an external clock, limited to 0 V to 5.5 V, defaulting to the FADJ frequency when no clock is present and to be tied to GND if unused.
7	UVLO/EN	input	Precision UVLO/enable input with a 1.15-V rising enable threshold, 0.985-V falling threshold, 165-mV voltage hysteresis, and a pin range of 0 V to min(VIN, 5.5 V).
8	OTP	input	Overtemperature protection setpoint pin where a resistor and 0.1-µF capacitor to GND set the OTP threshold from the remote thermal diode, and it is connected to GND if system OTP is not required.
9	D+	input	External temperature sense input for a 2N3904-type NPN remote thermal diode (base and collector shorted) used to compensate inductor DCR drift and provide system thermal shutdown.
10	D-	input	Return path for the external NPN thermal diode, to be routed as a differential pair with D+ and connected to GND.
11	PGOOD	output	Open-drain power-good output that goes low during fault or unregulated conditions, requires an external pullup, includes a 20-µs deglitch filter, and must not exceed 5.5 V.
12	VIN	power_in	Input voltage rail operating from 3.0 V to 20 V that provides feedforward and internal bias generation, to be decoupled locally with a 1-µF ceramic capacitor.
13	GND	power_in	Common ground for power and signal return, including low-side gate return, soft-start capacitor, OTP resistor, and frequency adjust resistor.
14	VDD	power_out	Subregulated 4.7-V bias supply rail (VDD range 2.6 V to 5.5 V) for internal and gate drive circuits, to be decoupled with a 10-µF ceramic capacitor and not used to drive auxiliary loads.
15	LG	output	Low-side MOSFET gate drive output that connects to the low-side N-FET gate.
16	SW	power_out	Power stage switch-node connection that also serves as the high-side N-FET gate driver return, tolerating negative spikes to -10 V and positive spikes to 30 V for up to 10 ns.
17	HG	output	High-side MOSFET gate drive output that connects to the high-side N-FET gate.
18	CBOOT	power_in	High-side bootstrap connection supplying the high-side N-FET gate driver, with a 100-nF ceramic capacitor between CBOOT and SW and spikes up to 35 V tolerated for 10 ns.
19	NC	unconnected	No connection; the datasheet says to connect this pin directly to GND.
20	NC	unconnected	No connection; the datasheet says to connect this pin directly to GND.
21	NC	unconnected	No connection; the datasheet says to connect this pin directly to GND.
22	NC	unconnected	No connection; the datasheet says to connect this pin directly to GND.
23	CS+	input	Noninverting input to the current-sense comparator for DCR-based overcurrent sensing, with CS+ to CS- limited to ±1 V.
24	CS-	input	Inverting input to the current-sense comparator, with 9.9 µA of nominal offset current at room temperature used to adjust the current-limit setpoint.
25	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	QFN-24-EP(4x4)
Category	Power Management ICs
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
FB pin voltage accuracy	VFB	594	600	606	mV		6
FB pin bias current	IFB	-165	0	165	nA	VFB = 0.65 V	6
Input undervoltage lockout	UVLO	2.6	2.7	2.8	V	VVIN rising, VVDD rising	6
Switching frequency	FSW	925	1050	1150	kHz	RFADJ = 4.12 kΩ	6
Switching frequency	FSW	435	500	555	kHz	RFADJ = 20 kΩ	6
Switching frequency	FSW	185	215	250	kHz	RFADJ = 95.3 kΩ	6
Minimum off-time	TOFF-MIN	110	150	190	ns	VFB = 0.5 V, FSW = 500 kHz	6
VDD subregulator output voltage	VDD	4.2	4.7	5.3	V	IVDD = 25 mA	6
Current limit comparator offset voltage	VCS_OFFSET	-3.5	0	3.5	mV		6
Current limit offset current	ICS	9.3	9.9	10.5	µA	VCS- = 3 V, ΔVBE = 59.4 mV, TJ = 25°C	7
Current limit offset current (D+ shorted to D-)	ICS	3.4	5	6.6	µA	VCS- = 3 V, D+ shorted to D-	7
ICS temperature coefficient	ICS-TC	160	187	212	nA/mV	Referenced to ΔVBE	7
Soft-start source current	ISS	1	3	5	µA	VSS/TRACK = 0 V	7
Overvoltage threshold	OVT	111	116.5	123	%	VFB rising, RS tied to GND	7
Undervoltage threshold	UVT	86	91	97	%	VFB rising, RS tied to GND	7
UVLO/EN logic low threshold	VUVLO1	0.94	0.985	1.03	V	VUVLO/EN falling	7
UVLO/EN logic high threshold	VUVLO2	1.11	1.15	1.18	V	VUVLO/EN rising	7
UVLO/EN voltage hysteresis	VUVLO-HYS	139	165	190	mV	VUVLO/EN falling	7
UVLO/EN pullup current, disabled	IUVLO1	0.8	1.8	2.7	µA	VUVLO/EN = 0 V	7
UVLO/EN pullup current, enabled	IUVLO2	5.5	10.5	15.5	µA	VUVLO/EN = 1.25 V	7
Remote thermal current	IOTP	13.5	14.6	15.5	µA	ΔVBE = 79.3 mV	8
IOTP temperature coefficient	IOTP-TC	158	187	213	nA/mV	Referenced to ΔVBE	8
OTP resistance, thermal shutdown	ROTP	-5		5	%	ROTP(nom) = 80.7 kΩ, ΔVBE = 79.3 mV, TJ = 125°C	8
Voltage on VIN, CS+, CS-, SW	VIN, CS+, CS-, SW	-0.3		22	V		5
Voltage on VDD, PGOOD	VDD, PGOOD	-0.3		6	V		5
Voltage on SS/TRACK, SYNC, FADJ, COMP, FB, RS	SS/TRACK, SYNC, FADJ, COMP, FB, RS	-0.3			V		5
Voltage on UVLO/EN	UVLO/EN	-0.3			V		5
Voltage on CBOOT	CBOOT	-0.3		24	V		5
Voltage CBOOT to SW	CBOOT to SW	-0.3		6	V		5
Voltage CS+ to CS-	CS+ to CS-	-1		1	V		5
Voltage on OTP, D+, D-	OTP, D+, D-	-0.3			V		5
Operating junction temperature	TJ	-40		150	°C		5
Input voltage (VIN tied to VDD)	VIN	3		5.5	V	VIN tied to VDD	5
Input voltage	VIN	3		20	V		5
SW pin voltage	SW	-0.3		20	V		5
VDD pin voltage	VDD	2.6	4.7	5.5	V		5
PGOOD pin voltage	PGOOD	0		5.5	V		5
UVLO/EN pin voltage	UVLO/EN	0			V		5
SS/TRACK pin voltage	SS/TRACK	0			V		5
SYNC pin voltage	SYNC	0		5.5	V		5
RS pin voltage	RS	-0.1		0.1	V		5
Operating junction temperature	TJ	-40		125	°C		5
Operating free-air temperature	TA	-40		125	°C		5
Junction-to-ambient thermal resistance	θJA		32.7		°C/W		6
Junction-to-case (top) thermal resistance	θJCtop		31.2		°C/W		6
Junction-to-board thermal resistance	θJB		11.2		°C/W		6
Junction-to-top characterization parameter	ψJT		0.2		°C/W		6
Junction-to-board characterization parameter	ψJB		11.2		°C/W		6
Junction-to-case (bottom) thermal resistance	θJCbot		1.4		°C/W		6

CAD (KiCad official)

Symbol: LM27403SQ
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: lm27403sq-etched.step / lm27403sq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm27403sq.step / lm27403sq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (56 pp, sha256 b9d9b331b0096516, retrieved 2026-10-30, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

LM27403SQ

Verified LM27403SQ

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README