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LTC6752HMS8-2#PBF
Public Made by Adomby adom
Analog Devices Pre-ordered Chips, MSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdownLTC6752HMS8-2#PBF
Analog Devices · Pre-ordered Chips · MSOP-8
LTC6752HMS8-2#PBF from Analog Devices, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Positive supply for the input stage of the LTC6752-2, with VCC to VEE specified from 2.45V to 5.25V. |
| 2 | +IN | input | Positive comparator input whose voltage range can go from VEE to VCC. |
| 3 | -IN | input | Negative comparator input whose voltage range can go from VEE to VCC. |
| 4 | SHDN | input | Active-low shutdown that must be taken to within 600mV of VEE to shut the part down (threshold 0.6V above VEE), and the comparator stays enabled when the pin is left unconnected. |
| 5 | LE/HYST | input | Adjusts hysteresis and latches the output when taken to within 300mV above VEE, and leaving it unconnected gives a typical hysteresis of 5mV. |
| 6 | VEE | power_in | Negative supply, normally tied to ground, which may be another voltage as long as the total supply constraints relative to VCC and VDD are maintained. |
| 7 | Q | output | Comparator output that is driven high when +IN is greater than -IN and driven low when +IN is less than -IN. |
| 8 | VDD | power_in | Positive supply for the output stage of the LTC6752-2, typically 1.71V to 3.5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-8 |
| Category | Interface ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Total Supply Voltage (VCC to VEE), LTC6752-2 | VCC to VEE | 5.5 | V | LTC6752-2/LTC6752-3/LTC6752-4 | 2 | ||
| Input Current (+IN, -IN, SHDN, LE/HYST) | -10 | 10 | mA | Note 2 | 2 | ||
| Output Current (Q, Q) | -50 | 50 | mA | Note 3 | 2 | ||
| Specified Temperature Range, LTC6752H | -40 | 125 | °C | LTC6752H (Note 4) | 2 | ||
| Storage Temperature Range | -65 | 125 | °C | 2 | |||
| Maximum Junction Temperature | TJMAX | 150 | °C | Note 3 | 2 | ||
| Lead Temperature Soldering | 300 | °C | 10s | 2 | |||
| Thermal Resistance, junction to ambient | θJA | 163 | °C/W | MS8 package (Note 3) | 2 | ||
| Supply Voltage, input stage (VCC - VEE) | VCC - VEE | 2.45 | 5.25 | V | LTC6752-2 input stage; l | 3 | |
| Output Stage Supply Voltage (VDD - VEE) | VDD - VEE | 1.71 | 3.5 | V | LTC6752-2; l | 3 | |
| Input Offset Voltage | VOS | -5.5 | 5.5 | mV | 3 | ||
| Input Offset Voltage | VOS | -8.5 | 8.5 | mV | l: over specified temperature range | 3 | |
| Input Offset Voltage Drift | TCVOS | 18 | µV/°C | l: over specified temperature range | 3 | ||
| Input Hysteresis Voltage | VHYST | 5 | mV | LE/HYST pin floating | 3 | ||
| Input Offset Current | IOS | -0.75 | 0.75 | µA | l: over specified temperature range | 3 | |
| Common Mode Rejection Ratio, low VCM region | CMRR_LVCM | 51 | 69 | dB | VCM = VEE, 0.2V to VCC, 1.5V | 3 | |
| Common Mode Rejection Ratio, low VCM region | CMRR_LVCM | 46 | dB | VCM = VEE, 0.2V to VCC, 1.5V; l | 3 | ||
| Common Mode Rejection Ratio, full range | CMRR_FR | 50 | 65 | dB | VCM = VEE, 0.2V to VCC + 0.1V | 3 | |
| Common Mode Rejection Ratio, full range | CMRR_FR | 45.5 | dB | VCM = VEE, 0.2V to VCC + 0.1V; l | 3 | ||
| Input Power Supply Rejection Ratio | PSRR_VCC | 59 | 74 | dB | VCM = 0.3V, VDD = 2.5V, VCC varied 2.45V to 5.25V | 4 | |
| Input Power Supply Rejection Ratio | PSRR_VCC | 57 | dB | VCM = 0.3V, VDD = 2.5V, VCC varied 2.45V to 5.25V; l | 4 | ||
| Output Power Supply Rejection Ratio | PSRR_VDD | 56 | 71 | dB | VCM = 0.3V, VDD varied 1.71V to 3.5V | 4 | |
| Output Power Supply Rejection Ratio | PSRR_VDD | 51 | dB | VCM = 0.3V, VDD varied 1.71V to 3.5V; l | 4 | ||
| Open Loop Gain | AVOL | 6000 | V/V | LTC6752-2, hysteresis removed (Note 12) | 4 | ||
| Output High Voltage (below VDD) | VOH | 130 | 260 | mV | ISOURCE = 8mA | 4 | |
| Output High Voltage (below VDD) | VOH | 340 | mV | ISOURCE = 8mA; l | 4 | ||
| Output Low Voltage (referred to VEE) | VOL | 200 | 340 | mV | ISINK = 8mA | 4 | |
| Output Low Voltage (referred to VEE) | VOL | 400 | mV | ISINK = 8mA; l | 4 | ||
| Output Short-Circuit Current, source | ISC | 16 | 30 | mA | Source | 4 | |
| Output Short-Circuit Current, source | ISC | 12 | mA | Source; l | 4 | ||
| Output Short-Circuit Current, sink | ISC | 15 | 22 | mA | Sink | 4 | |
| Output Short-Circuit Current, sink | ISC | 9 | mA | Sink; l | 4 | ||
| VCC Supply Current, device on (LTC6752-2) | IVCC | 1.9 | 2.25 | 2.5 | mA | LTC6752-2/LTC6752-3/LTC6752-4; l | 4 |
| VDD Supply Current, device on (LTC6752-2) | IVDD | 2.6 | 3.2 | 3.4 | mA | LTC6752-2/LTC6752-4; l | 4 |
| Total Supply Current, device on (LTC6752-2) | ITOTAL | 4.5 | 5 | 5.9 | mA | LTC6752-2/LTC6752-4; l | 4 |
| Rise/Fall Time | tR, tF | 1.2 | ns | 10% to 90% | 4 | ||
| Propagation Delay | tPD | 2.9 | 5 | ns | VOVERDRIVE = 50mV | 4 | |
| Propagation Delay | tPD | 5.5 | ns | VOVERDRIVE = 50mV; l | 4 | ||
| Propagation Delay Skew, rising to falling | tSKEW | 300 | ps | 4 | |||
| Overdrive Dispersion | tODD | 1.8 | ns | Overdrive varied 10mV to 125mV | 4 | ||
| Common Mode Dispersion | tCMD | 240 | ps | VCM varied VEE, 0.2V to VCC + 0.1V | 4 | ||
| Toggle Rate | TR | 280 | MHz | 100mVP-P input, LTC6752-2 | 4 | ||
| LE/HYST Pin Voltage, open circuit | VLE/HYST | 1.05 | 1.25 | 1.45 | V | Open circuit; l | 5 |
| Resistance Looking Into LE/HYST | RHYST | 15 | 20 | 25 | kΩ | LE/HYST pin voltage < open circuit value; l | 5 |
| Hysteresis Voltage | VHYST_LARGE | 40 | mV | VLE/HYST = 800mV | 5 | ||
| Latch Pin Voltage, latch guaranteed | VIL_LE | 0.3 | V | l | 5 | ||
| Latch Pin Voltage, hysteresis disabled | VIH_LE | 1.7 | V | Output not latched; l | 5 | ||
| Latch Pin Current High | IIH_LE | 30 | 72 | µA | VLE/HYST = 1.7V; l | 5 | |
| Latch Pin Current Low | IIL_LE | -70 | -47 | µA | VLE/HYST = 0.3V; l | 5 | |
| Latch Setup Time | tSETUP | -2 | ns | Note 10 | 5 | ||
| Latch Hold Time | tHOLD | 2 | ns | Note 10 | 5 | ||
| Latch to Output Delay | tPL | 7 | ns | 5 | |||
| Shutdown Mode Input Stage Supply Current | ISD_VCC | 400 | 585 | µA | VSHDN = 0.6V | 5 | |
| Shutdown Mode Input Stage Supply Current | ISD_VCC | 620 | µA | VSHDN = 0.6V; l | 5 | ||
| Shutdown Mode Output Stage Supply Current (LTC6752-2) | ISD_VDD | 185 | 340 | µA | VSHDN = 0.6V, LTC6752-2 | 5 | |
| Shutdown Mode Output Stage Supply Current (LTC6752-2) | ISD_VDD | 380 | µA | VSHDN = 0.6V, LTC6752-2; l | 5 | ||
| Shutdown Time, output Hi-Z | tSD | 80 | ns | 5 | |||
| Shutdown Pin Voltage High | VIH_SD | 1.3 | V | Part guaranteed powered on; l | 5 | ||
| Shutdown Pin Voltage Low | VIL_SD | 0.6 | V | Part guaranteed powered off; l | 5 | ||
| Wake-Up Time from Shutdown | tWAKEUP | 100 | ns | VOD = 100mV, output valid | 5 |
CAD (KiCad official)
- Symbol:
LTC6752HMS8-2#PBF - Footprint:
Package_SO:MSOP-8_3x3mm_P0.65mm - 3D model: MSOP-8 (KiCad packages3D, STEP)
- 3D model files:
ltc6752hms8-2-pbf-etched.step/ltc6752hms8-2-pbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ltc6752hms8-2-pbf.step/ltc6752hms8-2-pbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (30 pp, sha256
d0e3d938d1b220ae, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).