Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

MSP430FR2355TRHAR

Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-40-EP(6x6)

MSP430FR2355TRHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.1 bidirectional General-purpose I/O P1.1 (LVCMOS, 3.0 V) that can also serve as UCB0CLK, ACLK output, OA0O, COMP0.1 or analog input A1.
2 P1.0 bidirectional General-purpose I/O P1.0 (LVCMOS, 3.0 V) that can also serve as UCB0STE, SMCLK output, COMP0.0, analog input A0 or the Veref+ reference input.
3 TEST/SBWTCK input Test-mode pin that doubles as the Spy-Bi-Wire clock SBWTCK; it always has an internal pulldown enabled, so leave it open when unused.
4 RST/NMI/SBWTDIO bidirectional Active-low reset (RST), non-maskable interrupt input (NMI) and Spy-Bi-Wire data (SBWTDIO); when unused, use a 47-kΩ pullup to DVCC or the internal pullup with a 10-nF (or 1.1-nF) pulldown.
5 DVCC power_in Primary supply pin for digital and analog modules, specified at 1.8 V to 3.6 V, with a 4.7-µF to 10-µF capacitor recommended at this pin.
6 DVSS power_in Ground (0 V) supply pin for the device; the exposed thermal pad must also be connected to VSS.
7 P2.7/TB0CLK/XIN bidirectional General-purpose I/O P2.7 that can also serve as the TB0CLK timer clock input or the XIN crystal oscillator input.
8 P2.6/MCLK/XOUT bidirectional General-purpose I/O P2.6 that can also serve as the MCLK output or the XOUT crystal oscillator output.
9 P2.5/COMP1.0 bidirectional General-purpose I/O P2.5 that can also serve as eCOMP1 comparator input COMP1.0 (analog).
10 P2.4/COMP1.1 bidirectional General-purpose I/O P2.4 that can also serve as eCOMP1 comparator input COMP1.1 (analog).
11 P4.7/UCB1SOMI/UCB1SCL bidirectional General-purpose I/O P4.7 that can also serve as eUSCI_B1 SPI slave-out (UCB1SOMI) or I2C clock (UCB1SCL).
12 P4.6/UCB1SIMO/UCB1SDA bidirectional General-purpose I/O P4.6 that can also serve as eUSCI_B1 SPI slave-in/master-out (UCB1SIMO) or I2C data (UCB1SDA).
13 P4.5/UCB1CLK bidirectional General-purpose I/O P4.5 that can also serve as the eUSCI_B1 SPI clock (UCB1CLK).
14 P4.4/UCB1STE bidirectional General-purpose I/O P4.4 that can also serve as the eUSCI_B1 SPI STE signal (UCB1STE).
15 P6.1/TB3.2 bidirectional General-purpose I/O P6.1 that can also serve as Timer_B3 capture/compare channel TB3.2.
16 P6.0/TB3.1 bidirectional General-purpose I/O P6.0 that can also serve as Timer_B3 capture/compare channel TB3.1.
17 P4.3/UCA1TXD/UCA1SIMO bidirectional General-purpose I/O P4.3 that can also serve as eUSCI_A1 UART transmit (UCA1TXD) or SPI SIMO (UCA1SIMO).
18 P4.2/UCA1RXD/UCA1SOMI bidirectional General-purpose I/O P4.2 that can also serve as eUSCI_A1 UART receive (UCA1RXD) or SPI SOMI (UCA1SOMI).
19 P4.1/UCA1CLK bidirectional General-purpose I/O P4.1 that can also serve as the eUSCI_A1 clock (UCA1CLK).
20 P4.0/UCA1STE/ISOTXD/ISORXD bidirectional General-purpose I/O P4.0 that can also serve as the eUSCI_A1 STE signal (UCA1STE) or the ISO transmit/receive signals (ISOTXD/ISORXD).
21 P2.3/TB1TRG bidirectional General-purpose I/O P2.3 that can also serve as the TB1 external trigger input (TB1TRG).
22 P2.2/TB1CLK bidirectional General-purpose I/O P2.2 that can also serve as the Timer_B1 clock input (TB1CLK).
23 P2.1/TB1.2/COMP1.O bidirectional General-purpose I/O P2.1 that can also serve as Timer_B1 channel TB1.2 or eCOMP1 comparator output COMP1.O.
24 P2.0/TB1.1/COMP0.O bidirectional General-purpose I/O P2.0 that can also serve as Timer_B1 channel TB1.1 or eCOMP0 comparator output COMP0.O.
25 P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/OA1+/A7/VREF+ bidirectional General-purpose I/O P1.7 that can also serve as eUSCI_A0 UART transmit/SPI SIMO, Timer_B0 channel TB0.2, JTAG TDO, SAC1 non-inverting input OA1+, ADC input A7 or VREF+.
26 P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/OA1-/A6 bidirectional General-purpose I/O P1.6 that can also serve as eUSCI_A0 UART receive/SPI SOMI, Timer_B0 channel TB0.1, JTAG TDI/TCLK, SAC1 inverting input OA1- or ADC input A6.
27 P1.5/UCA0CLK/TMS/OA1O/A5 bidirectional General-purpose I/O P1.5 that can also serve as eUSCI_A0 clock (UCA0CLK), JTAG TMS, SAC1 output OA1O or ADC input A5.
28 P1.4/UCA0STE/TCK/A4 bidirectional General-purpose I/O P1.4 that can also serve as eUSCI_A0 STE, JTAG TCK or ADC input A4.
29 P3.7/OA3+ bidirectional General-purpose I/O P3.7 that can also serve as SAC3 non-inverting op-amp input OA3+ (MSP430FR235x only).
30 P3.6/OA3- bidirectional General-purpose I/O P3.6 that can also serve as SAC3 inverting op-amp input OA3- (MSP430FR235x only).
31 P3.5/OA3O bidirectional General-purpose I/O P3.5 that can also serve as SAC3 op-amp output OA3O (MSP430FR235x only).
32 P3.4/SMCLK bidirectional General-purpose I/O P3.4 that can also serve as the SMCLK clock output.
33 P5.1/TB2.2/MFM.TX/A9 bidirectional General-purpose I/O P5.1 that can also serve as Timer_B2 channel TB2.2, Manchester module transmit (MFM.TX) or ADC input A9.
34 P5.0/TB2.1/MFM.RX/A8 bidirectional General-purpose I/O P5.0 that can also serve as Timer_B2 channel TB2.1, Manchester module receive (MFM.RX) or ADC input A8.
35 P3.3/OA2+ bidirectional General-purpose I/O P3.3 that can also serve as SAC2 non-inverting op-amp input OA2+ (MSP430FR235x only).
36 P3.2/OA2- bidirectional General-purpose I/O P3.2 that can also serve as SAC2 inverting op-amp input OA2- (MSP430FR235x only).
37 P3.1/OA2O bidirectional General-purpose I/O P3.1 that can also serve as SAC2 op-amp output OA2O (MSP430FR235x only).
38 P3.0/MCLK bidirectional General-purpose I/O P3.0 that can also serve as the MCLK clock output.
39 P1.3/UCB0SOMI/UCB0SCL/OA0+/A3 bidirectional General-purpose I/O P1.3 that can also serve as eUSCI_B0 SPI SOMI or I2C clock (UCB0SCL), SAC0 non-inverting input OA0+ or ADC input A3.
40 P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/Veref- bidirectional General-purpose I/O P1.2 (reset default function) that can also serve as eUSCI_B0 SPI SIMO or I2C data (UCB0SDA), Timer_B0 trigger TB0TRG, SAC0 inverting input OA0-, ADC input A2 or the Veref- reference input.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-40-EP(6x6)
Category Embedded Processors & Controllers
Pins 41

CAD (KiCad official)

  • Symbol: MSP430FR2355TRHAR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: msp430fr2355trhar-etched.step / msp430fr2355trhar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); msp430fr2355trhar.step / msp430fr2355trhar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (152 pp, sha256 f1ebe8a259a8e556, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF