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HT8563ARZ

Public Made by Adom

by adom

HTCSEMI Real Time Clocks, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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HT8563ARZ

HTCSEMI · Real Time Clocks · SOIC-8

HT8563ARZ from HTCSEMI, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OSCI input Pin for connection of the 32.768 kHz quartz resonator, with an internal load capacitance of 12 pF; it can also be driven by an external 32.768 kHz oscillator.
2 OSCO output Pin for connection of the 32.768 kHz quartz resonator; it is left unconnected when OSCI is driven by an external oscillator.
3 INT output Interruption output, activated by an alarm match or by timer countdown to zero; the output voltage is limited to 0 to 5.5 V (absolute limits -0.5 to 6.5 V).
4 VSS power_in Common ground pin; all voltages are referenced to this pin.
5 SDA bidirectional Serial data input/output of the double-wire I2C-type bus; it is an open-drain output that requires an external pull-up resistor.
6 SCL input Serial clock input for the double-wire bus, operating up to 400 kHz.
7 CLKOUT output Programmable frequency output enabled by bit FE; it is open-drain and requires an external pull-up resistor.
8 VDD power_in Supply pin, +1 V to +5.5 V for timekeeping; serial interface access is not guaranteed below 1.8 V.

Key specifications

Parameter Value
Manufacturer HTCSEMI
Package SOIC-8
Category Clock/Timing
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (norm) VDD 1 5.5 V Norm range, not less / not over 2
Supply voltage (limit permissible) VDD -0.5 6.5 V Limit permissible range 2
Dissipated power Ptot 300 mWt Limit permissible 2
Input voltage SCL, SDA, OSCI (norm) VI 0 5.5 V Norm range 2
Input voltage SCL, SDA, OSCI (limit permissible) VI -0.5 6.5 V Limit permissible range 2
Output voltage CLKOUT, INT (norm) VO 0 5.5 V Norm range 2
Output voltage CLKOUT, INT (limit permissible) VO -0.5 6.5 V Limit permissible range 2
Direct input or output current via any pin IIO -10 10 mА Limit permissible 2
Operating temperature range TA -40 85 °C 2
Supply voltage, I2C bus active VDD 1.8 5.5 V I2C bus active; FSCL = 400 kHz 2
Supply voltage, non-active mode VDD 1 5.5 V in the non-active mode 2
Input leakage current ILI 1 µА VIN = VDD; VIN = VSS 2
Output leakage current ILO 1 µА VOUT = VDD; VOUT = VSS 2
Consumption current IDD1 800 µА CLKOUT-off, FSCL = 400 kHz 2
Consumption current IDD1 200 µА CLKOUT-off, FSCL = 100 kHz 2
Consumption current IDD1 0.55 µА CLKOUT-off, FSCL = 0 kHz, VDD = 5V 2
Consumption current IDD1 0.45 µА CLKOUT-off, FSCL = 0 kHz, VDD = 2V 2
Low level input voltage VIL 0.3 ×VDD Printed as VSS to 0.3VDD; min is VSS (not numeric) 2
High level input voltage VIH 0.7 ×VDD Printed as 0.7VDD to VDD; max is VDD (not numeric) 2
Low level output current at pin CLKOUT IOL1 1 mА VOL = 0.4 V, VDD = 5 V 2
High level output current at pin CLKOUT IOH1 1 mА VOH = 4.6 V, VDD = 5 V 2
Low level output current at pin INT IOL2 1 mА VOL = 0.4 V, VDD = 5 V 2
Low level output current at pin SDA IOL3 3 mА VOL = 0.4 V, VDD = 5 V 3
Supply low level detected by the circuit VLOW 1 V 3
Cycle frequency SCL fSCL 400 kHz TA = -40...+85°C, VCC = 4.5-5.5 V 3
Time of bus vacant condition between STOP and START tBUF 4.7 usec TA = -40...+85°C, VCC = 4.5-5.5 V 3
Hold time (repeated) of condition START tHD:STA 0.6 usec TA = -40...+85°C, VCC = 4.5-5.5 V 3
Low condition duration of SCL pulse tLOW 1.3 usec TA = -40...+85°C, VCC = 4.5-5.5 V 3
High condition duration of SCL pulse tHIGH 0.6 usec TA = -40...+85°C, VCC = 4.5-5.5 V 3
Presetting time for repeated condition START tSU:STA 0.6 usec TA = -40...+85°C, VCC = 4.5-5.5 V 3
Data hold time tHD:DAT 0 usec TA = -40...+85°C, VCC = 4.5-5.5 V 3
Data presetting time tSU:DAT 100 nsec TA = -40...+85°C, VCC = 4.5-5.5 V 3
Rise time for signals SDA and SCL tR 300 nsec TA = -40...+85°C, VCC = 4.5-5.5 V 3
Drop time for signals SDA and SCL tF 300 nsec TA = -40...+85°C, VCC = 4.5-5.5 V 3
Presetting time for condition STOP tSU:STO 0.6 usec TA = -40...+85°C, VCC = 4.5-5.5 V 3
Total capacitance load on each bus line CB 400 pF TA = -40...+85°C, VCC = 4.5-5.5 V 3
Capacity input/output CI/O 10 pF TA = -40...+85°C, VCC = 4.5-5.5 V 3
Load capacitance of the quartz resonator CLX 12.5 pF TA = -40...+85°C, VCC = 4.5-5.5 V 3

CAD (KiCad official)

  • Symbol: HT8563ARZ
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ht8563arz-etched.step / ht8563arz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ht8563arz.step / ht8563arz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HTCSEMI datasheet (11 pp, sha256 f84e780cf3796e05, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF