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BQ7695203PFBR

Texas Instruments · Battery Management · TQFP-48(7x7)

BQ7695203PFBR from Texas Instruments, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VC15 input Sense voltage input for the 15th cell from the bottom of the stack, which also serves as balance current input for that cell and return balance current for the 16th cell.
2 VC14 input Sense voltage input for the 14th cell from the bottom of the stack, which also serves as balance current input for that cell and return balance current for the 15th cell.
3 VC13 input Sense voltage input for the 13th cell from the bottom of the stack, which also serves as balance current input for that cell and return balance current for the 14th cell.
4 VC12 input Sense voltage input for the 12th cell from the bottom of the stack, which also serves as balance current input for that cell and return balance current for the 13th cell.
5 VC11 input Sense voltage input for the 11th cell from the bottom of the stack, which also serves as balance current input for that cell and return balance current for the 12th cell.
6 VC10 input Sense voltage input for the 10th cell from the bottom of the stack, which also serves as balance current input for that cell and return balance current for the 11th cell.
7 VC9 input Sense voltage input for the 9th cell from the bottom of the stack, which also serves as balance current input for that cell and return balance current for the 10th cell.
8 VC8 input Sense voltage input for the 8th cell from the bottom of the stack, which also serves as balance current input for that cell and return balance current for the 9th cell.
9 VC7 input Sense voltage input for the 7th cell from the bottom of the stack, which also serves as balance current input for that cell and return balance current for the 8th cell.
10 VC6 input Sense voltage input for the 6th cell from the bottom of the stack, which also serves as balance current input for that cell and return balance current for the 7th cell.
11 VC5 input Sense voltage input for the 5th cell from the bottom of the stack, which also serves as balance current input for that cell and return balance current for the 6th cell.
12 VC4 input Sense voltage input for the 4th cell from the bottom of the stack, which also serves as balance current input for that cell and return balance current for the 5th cell.
13 VC3 input Sense voltage input for the 3rd cell from the bottom of the stack, which also serves as balance current input for that cell and return balance current for the 4th cell.
14 VC2 input Sense voltage input for the 2nd cell from the bottom of the stack, which also serves as balance current input for that cell and return balance current for the 3rd cell.
15 VC1 input Sense voltage input for the 1st cell from the bottom of the stack, which also serves as balance current input for that cell and return balance current for the 2nd cell.
16 VC0 input Sense voltage input for the negative terminal of the 1st cell from the bottom of the stack, which also returns balance current for that cell.
17 VSS power_in Device ground.
18 SRP input Analog input to the internal coulomb counter for integrating the small voltage between SRP and SRN, where SRP is the top of the sense resistor and a charging current produces a positive voltage at SRP relative to SRN.
19 NC unconnected This pin is not connected to silicon.
20 SRN input Analog input to the internal coulomb counter for integrating the small voltage between SRP and SRN, where SRN is the bottom of the sense resistor.
21 TS1 bidirectional Thermistor input or general-purpose ADC input (open-drain / analog I/O).
22 TS2 bidirectional Thermistor input that also provides wakeup from SHUTDOWN mode, or general-purpose ADC input.
23 TS3 bidirectional Thermistor input or general-purpose ADC input (open-drain / analog I/O).
24 REG18 power_out Internal 1.8 V LDO output, for internal use only.
25 ALERT bidirectional Multifunction pin configurable as ALERT output, HDQ I/O, thermistor input, general-purpose ADC input, or general-purpose digital output.
26 SCL bidirectional Multifunction open-drain pin that serves as the I2C clock SCL or as SPI_SCLK.
27 SDA bidirectional Multifunction open-drain pin that serves as the I2C data SDA or as SPI_MISO.
28 HDQ bidirectional Multifunction pin that serves as HDQ I/O, SPI_MOSI, thermistor input, general-purpose ADC input, or general-purpose digital output.
29 CFETOFF bidirectional Multifunction pin that serves as CHG FET disable input (CFETOFF), SPI_CS, thermistor input, general-purpose ADC input, or general-purpose digital output.
30 DFETOFF bidirectional Multifunction pin that serves as DSG FET disable input (DFETOFF or BOTHOFF), thermistor input, general-purpose ADC input, or general-purpose digital output.
31 DCHG bidirectional Multifunction pin that outputs a logic-level signal for the fault that would disable the CHG driver, or serves as thermistor input, general-purpose ADC input, or general-purpose digital output.
32 DDSG bidirectional Multifunction pin that outputs a logic-level signal for the fault that would disable the DSG driver, or serves as thermistor input, general-purpose ADC input, or general-purpose digital output.
33 RST_SHUT input Digital input for reset or shutdown; holding it high resets most digital logic immediately and holding it high for 1 second transitions the device into SHUTDOWN mode.
34 REG2 power_out Second LDO output, programmable to 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V.
35 REG1 power_out First LDO output, programmable to 1.8 V, 2.5 V, 3.0 V, 3.3 V, or 5.0 V.
36 REGIN input Input pin for the REG1 and REG2 LDOs.
37 BREG output Base control signal for the external pre-regulator transistor.
38 FUSE bidirectional Fuse sense and drive pin that drives the gate of an NFET to blow a chemical fuse when a permanent fail occurs and otherwise stays high-impedance.
39 PDSG output Predischarge PFET control output.
40 PCHG output Precharge PFET control output.
41 LD bidirectional Load detect pin, with an internal pullup from BAT used for load detection.
42 PACK input Pack sense input pin.
43 DSG output NMOS discharge FET drive output.
44 NC unconnected This pin is not connected to silicon.
45 CHG output NMOS charge FET drive output.
46 CP1 bidirectional Charge pump capacitor pin, which should be connected to BAT if the charge pump is not used.
47 BAT power_in Primary power supply input pin, with supply voltage up to 85 V absolute maximum (VSS+85 V).
48 VC16 input Sense voltage input for the 16th cell from the bottom of the stack, which also serves as its balance current input and the top-of-stack measurement point.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-48(7x7)
Category Power Management (PMIC)
Pins 48

CAD (KiCad official)

  • Symbol: BQ7695203PFBR
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: bq7695203pfbr-etched.step / bq7695203pfbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); bq7695203pfbr.step / bq7695203pfbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (88 pp, sha256 0a51de7a50876154, retrieved 2026-10-12, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF