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STL60P4LLF6-VB
Public Made by Adomby adom
VBsemi Elec MOSFETs, DFN5x6-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownSTL60P4LLF6-VB
VBsemi Elec · MOSFETs · DFN5x6-8
STL60P4LLF6-VB from VBsemi Elec, in a DFN5x6-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source of the P-channel MOSFET, tied with pins 2 and 3; pin 1 is marked by a dot on the package. |
| 2 | S | passive | Source of the P-channel MOSFET, tied with pins 1 and 3. |
| 3 | S | passive | Source of the P-channel MOSFET, tied with pins 1 and 2. |
| 4 | G | input | Gate of the P-channel MOSFET; gate-source voltage limit is ±20 V, with RDS(on) specified at VGS = -10 V and -4.5 V. |
| 5 | D | passive | Drain of the P-channel MOSFET, tied with pins 6, 7 and 8; drain-source voltage is -30 V max. |
| 6 | D | passive | Drain of the P-channel MOSFET, tied with pins 5, 7 and 8. |
| 7 | D | passive | Drain of the P-channel MOSFET, tied with pins 5, 6 and 8. |
| 8 | D | passive | Drain of the P-channel MOSFET, tied with pins 5, 6 and 7. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | VBsemi Elec |
| Package | DFN5x6-8 |
| Category | Transistors/Thyristors |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | -30 | V | TA = 25 °C | 1 | ||
| Gate-Source Voltage | VGS | -20 | 20 | V | TA = 25 °C | 1 | |
| Continuous Drain Current | ID | -120 | A | TC = 25 °C, TJ = 150 °C, package limited | 1 | ||
| Continuous Drain Current | ID | -100 | A | TC = 70 °C, TJ = 150 °C, package limited | 1 | ||
| Continuous Drain Current | ID | -31.6 | A | TA = 25 °C, TJ = 150 °C | 1 | ||
| Continuous Drain Current | ID | -25.3 | A | TA = 70 °C, TJ = 150 °C | 1 | ||
| Pulsed Drain Current | IDM | -280 | A | 1 | |||
| Continuous Source-Drain Diode Current | IS | -80 | A | TC = 25 °C | 1 | ||
| Continuous Source-Drain Diode Current | IS | -56 | A | TA = 25 °C | 1 | ||
| Single Pulse Avalanche Current | IAS | -60 | A | L = 0.1 mH | 1 | ||
| Single Pulse Avalanche Energy | EAS | 160 | mJ | L = 0.1 mH | 1 | ||
| Maximum Power Dissipation | PD | 83 | W | TC = 70 °C | 1 | ||
| Maximum Power Dissipation | PD | 6.95 | W | TA = 25 °C | 1 | ||
| Maximum Power Dissipation | PD | 5 | W | TA = 70 °C | 1 | ||
| Operating Junction and Storage Temperature Range | TJ, Tstg | -55 | 150 | °C | 1 | ||
| Soldering Peak Temperature | 260 | °C | 1 | ||||
| Junction-to-Ambient Thermal Resistance | RthJA | 15 | 20 | °C/W | t ≤ 10 s | 1 | |
| Junction-to-Case (Drain) Thermal Resistance | RthJC | 0.9 | 1.2 | °C/W | Steady State | 1 | |
| Drain-Source Breakdown Voltage | VDS | -30 | V | VGS = 0 V, ID = - 250 µA | 2 | ||
| Gate-Source Threshold Voltage | VGS(th) | -1 | -3 | V | VDS = VGS, ID = - 250 µA | 2 | |
| Gate-Source Leakage | IGSS | -100 | 100 | nA | VDS = 0 V, VGS = ± 20 V | 2 | |
| Zero Gate Voltage Drain Current | IDSS | -1 | µA | VDS = - 30 V, VGS = 0 V | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | -10 | µA | VDS = - 30 V, VGS = 0 V, TJ = 55 °C | 2 | ||
| On-State Drain Current | ID(on) | -30 | A | VDS = - 5 V, VGS = - 10 V | 2 | ||
| Body Diode Voltage | VSD | -0.54 | -1.1 | V | IS = - 5 A | 2 | |
| Continuous Source-Drain Diode Current | IS | 100 | A | TC = 25 °C | 2 | ||
| Pulse Diode Forward Current | ISM | 120 | A | 2 | |||
| Body Diode Reverse Recovery Time | trr | 50 | 100 | ns | IF = 3.5 A, dI/dt = 100 A/µs, TJ = 25 °C | 2 | |
| Body Diode Reverse Recovery Charge | Qrr | 65 | 130 | nC | IF = 3.5 A, dI/dt = 100 A/µs, TJ = 25 °C | 2 | |
| Turn-On Delay Time | td(on) | 25 | 40 | ns | VDD = - 15 V, RL = 15 Ω, ID ≅ - 1.0 A, VGEN = - 10 V, Rg = 1 Ω | 2 | |
| Rise Time | tr | 15 | 30 | ns | VDD = - 15 V, RL = 15 Ω, ID ≅ - 1.0 A, VGEN = - 10 V, Rg = 1 Ω | 2 | |
| Turn-Off Delay Time | td(off) | 110 | 170 | ns | VDD = - 15 V, RL = 15 Ω, ID ≅ - 1.0 A, VGEN = - 10 V, Rg = 1 Ω | 2 | |
| Fall Time | tf | 30 | 50 | ns | VDD = - 15 V, RL = 15 Ω, ID ≅ - 1.0 A, VGEN = - 10 V, Rg = 1 Ω | 2 | |
| Turn-On Delay Time | td(on) | 110 | 170 | ns | VDD = - 15 V, RL = 15 Ω, ID ≅ - 1.0 A, VGEN = - 4.5 V, Rg = 1 Ω | 2 | |
| Rise Time | tr | 100 | 150 | ns | VDD = - 15 V, RL = 15 Ω, ID ≅ - 1.0 A, VGEN = - 4.5 V, Rg = 1 Ω | 2 | |
| Turn-Off Delay Time | td(off) | 100 | 150 | ns | VDD = - 15 V, RL = 15 Ω, ID ≅ - 1.0 A, VGEN = - 4.5 V, Rg = 1 Ω | 2 | |
| Fall Time | tf | 50 | 75 | ns | VDD = - 15 V, RL = 15 Ω, ID ≅ - 1.0 A, VGEN = - 4.5 V, Rg = 1 Ω | 2 | |
| Gate Resistance | Rg | 1.9 | Ω | f = 1 MHz | 2 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | d. The DFN5x6 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cann | 1 |
CAD (KiCad official)
- Symbol:
STL60P4LLF6-VB - Footprint:
Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm - 3D model: DFN5x6-8 (KiCad packages3D, STEP)
- 3D model files:
stl60p4llf6-vb-etched.step/stl60p4llf6-vb-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);stl60p4llf6-vb.step/stl60p4llf6-vb.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: VBsemi Elec datasheet (8 pp, sha256
f7dd876a6359faa3, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).