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SN74LV132ADR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LV132ADR
Texas Instruments · Logic Gates · SOIC-14
SN74LV132ADR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Data input 1A of NAND gate 1; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC. |
| 2 | 1B | input | Data input 1B of NAND gate 1; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC. |
| 3 | 1Y | output | Output 1Y of NAND gate 1; load current should not exceed 25 mA per output and the output should not be pulled above VCC. |
| 4 | 2A | input | Data input 2A of NAND gate 2; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC. |
| 5 | 2B | input | Data input 2B of NAND gate 2; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC. |
| 6 | 2Y | output | Output 2Y of NAND gate 2; load current should not exceed 25 mA per output and the output should not be pulled above VCC. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 3Y | output | Output 3Y of NAND gate 3; load current should not exceed 25 mA per output and the output should not be pulled above VCC. |
| 9 | 3A | input | Data input 3A of NAND gate 3; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC. |
| 10 | 3B | input | Data input 3B of NAND gate 3; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC. |
| 11 | 4Y | output | Output 4Y of NAND gate 4; load current should not exceed 25 mA per output and the output should not be pulled above VCC. |
| 12 | 4A | input | Data input 4A of NAND gate 4; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC. |
| 13 | 4B | input | Data input 4B of NAND gate 4; Schmitt-trigger input that is overvoltage tolerant up to 5.5 V at any valid VCC. |
| 14 | VCC | power_in | Supply voltage, recommended operating range 2 V to 5.5 V; bypass with a 0.1 µF capacitor placed as close to the pin as possible. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74LV132ADR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
sn74lv132adr-etched.step/sn74lv132adr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lv132adr.step/sn74lv132adr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
eb436a12dc7197d7, retrieved 2026-10-08, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).