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TLV9164IDR
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Texas Instruments Operational Amplifier, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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README
markdownTLV9164IDR
Texas Instruments · Operational Amplifier · SOIC-14
TLV9164IDR from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT1 | output | Output of channel 1; the datasheet describes a rail-to-rail output and states that the output can be shorted continuously to ground (one amplifier per package) under the absolute maximum ratings. |
| 2 | IN1- | input | Inverting input of channel 1; the common-mode voltage must stay within V- to V+ and input current is limited to 10 mA when the input is driven more than 0.5 V beyond the rails. |
| 3 | IN1+ | input | Noninverting input of channel 1; the common-mode voltage must stay within V- to V+ and input current is limited to 10 mA when the input is driven more than 0.5 V beyond the rails. |
| 4 | V+ | power_in | Positive (highest) power supply; the recommended supply voltage (V+) - (V-) is 2.7 V to 16 V, with an absolute maximum of 20 V. |
| 5 | IN2+ | input | Noninverting input of channel 2; the common-mode voltage must stay within V- to V+ and input current is limited to 10 mA when the input is driven more than 0.5 V beyond the rails. |
| 6 | IN2- | input | Inverting input of channel 2; the common-mode voltage must stay within V- to V+ and input current is limited to 10 mA when the input is driven more than 0.5 V beyond the rails. |
| 7 | OUT2 | output | Output of channel 2; the datasheet describes a rail-to-rail output and states that the output can be shorted continuously to ground (one amplifier per package) under the absolute maximum ratings. |
| 8 | OUT3 | output | Output of channel 3; the datasheet describes a rail-to-rail output and states that the output can be shorted continuously to ground (one amplifier per package) under the absolute maximum ratings. |
| 9 | IN3- | input | Inverting input of channel 3; the common-mode voltage must stay within V- to V+ and input current is limited to 10 mA when the input is driven more than 0.5 V beyond the rails. |
| 10 | IN3+ | input | Noninverting input of channel 3; the common-mode voltage must stay within V- to V+ and input current is limited to 10 mA when the input is driven more than 0.5 V beyond the rails. |
| 11 | V- | power_in | Negative (lowest) power supply; this is the reference for the recommended supply span of 2.7 V to 16 V and the common-mode range, and is labeled V± in the pinout figure. |
| 12 | IN4+ | input | Noninverting input of channel 4; the common-mode voltage must stay within V- to V+ and input current is limited to 10 mA when the input is driven more than 0.5 V beyond the rails. |
| 13 | IN4- | input | Inverting input of channel 4; the common-mode voltage must stay within V- to V+ and input current is limited to 10 mA when the input is driven more than 0.5 V beyond the rails. |
| 14 | OUT4 | output | Output of channel 4; the datasheet describes a rail-to-rail output and states that the output can be shorted continuously to ground (one amplifier per package) under the absolute maximum ratings. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Amplifiers/Comparators |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Absolute maximum supply voltage, VS = (V+) – (V–) | VS | 0 | 20 | V | 7 | ||
| Absolute maximum signal input current | -10 | 10 | mA | Signal input pins | 7 | ||
| Absolute maximum operating ambient temperature | TA | -55 | 150 | °C | 7 | ||
| Absolute maximum junction temperature | TJ | 150 | °C | 7 | |||
| Absolute maximum storage temperature | Tstg | -65 | 150 | °C | 7 | ||
| Recommended supply voltage, (V+) – (V–) | VS | 2.7 | 16 | V | 7 | ||
| Recommended specified temperature | TA | -40 | 125 | °C | 7 | ||
| Input offset voltage | VOS | -1 | 0.21 | 1 | mV | VCM = V– | 9 |
| Input offset voltage over temperature | VOS | -1.2 | 1.2 | mV | TA = –40°C to 125°C | 9 | |
| Input offset voltage vs power supply (TLV9164) | PSRR | -2.2 | 0.45 | 2.2 | μV/V | TLV9164, VCM = V–, VS = 5 V to 16 V | 9 |
| Input offset voltage vs power supply over temperature (TLV9164) | PSRR | -3.8 | 0.45 | 3.8 | μV/V | TA = –40°C to 125°C | 9 |
| Input offset voltage vs power supply, 2.7 V to 16 V | PSRR | -12 | 2 | 12 | μV/V | TLV9161, TLV9162, TLV9164, VCM = V–, VS = 2.7 V to 16 V; TA = –40°C to 125°C | 9 |
| Common-mode rejection ratio (PMOS pair, VS = 16 V) | CMRR | 85 | 110 | dB | VS = 16 V, V– < VCM < (V+) – 2 V (PMOS pair), TA = –40°C to 125°C | 9 | |
| Common-mode rejection ratio (PMOS pair, VS = 5 V) | CMRR | 75 | 98 | dB | VS = 5 V, V– < VCM < (V+) – 2 V (PMOS pair) | 9 | |
| Open-loop voltage gain, VS = 16 V | AOL | 120 | 136 | dB | VS = 16 V, VCM = VS / 2, (V–) + 0.1 V < VO < (V+) – 0.1 V | 9 | |
| Open-loop voltage gain over temperature, VS = 16 V | AOL | 136 | dB | TA = –40°C to 125°C | 9 | ||
| Open-loop voltage gain, VS = 5 V | AOL | 104 | 125 | dB | VS = 5 V, VCM = VS / 2, (V–) + 0.1 V < VO < (V+) – 0.1 V | 9 | |
| Open-loop voltage gain over temperature, VS = 5 V | AOL | 125 | dB | TA = –40°C to 125°C | 9 | ||
| Open-loop voltage gain, VS = 2.7 V | AOL | 90 | 105 | dB | VS = 2.7 V, VCM = VS / 2, (V–) + 0.1 V < VO < (V+) – 0.1 V | 9 | |
| Open-loop voltage gain over temperature, VS = 2.7 V | AOL | 105 | dB | TA = –40°C to 125°C | 9 | ||
| Output voltage swing from rail, RL = 10 kΩ, VS = 16 V | 25 | 60 | mV | VS = 16 V, RL = 10 kΩ | 11 | ||
| Output voltage swing from rail, RL = 2 kΩ, VS = 16 V | 85 | 300 | mV | VS = 16 V, RL = 2 kΩ | 11 | ||
| Output voltage swing from rail, RL = 10 kΩ, VS = 2.7 V | 5 | 20 | mV | VS = 2.7 V, RL = 10 kΩ | 11 | ||
| Output voltage swing from rail, RL = 2 kΩ, VS = 2.7 V | 20 | 50 | mV | VS = 2.7 V, RL = 2 kΩ | 11 | ||
| Quiescent current per amplifier (TLV9164) | IQ | 2.4 | 2.8 | mA | TLV9164, IO = 0 A | 11 | |
| Quiescent current per amplifier over temperature | IQ | 2.84 | mA | TA = –40°C to 125°C | 11 | ||
| Thermal resistance, junction-to-ambient, D (SOIC-14) | RθJA | 99 | °C/W | Quad channel, D (SOIC) 14 pins | 8 | ||
| Thermal resistance, junction-to-case (top), D (SOIC-14) | RθJC(top) | 55.1 | °C/W | Quad channel, D (SOIC) 14 pins | 8 | ||
| Thermal resistance, junction-to-board, D (SOIC-14) | RθJB | 54.8 | °C/W | Quad channel, D (SOIC) 14 pins | 8 | ||
| Junction-to-top characterization parameter, D (SOIC-14) | ψJT | 16.7 | °C/W | Quad channel, D (SOIC) 14 pins | 8 | ||
| Junction-to-board characterization parameter, D (SOIC-14) | ψJB | 54.4 | °C/W | Quad channel, D (SOIC) 14 pins | 8 | ||
| Output voltage swing from rail, no load, VS = 16 V | 6 | mV | VS = 16 V, RL = no load | 11 | |||
| Output voltage swing from rail, no load, VS = 2.7 V | 0.5 | mV | VS = 2.7 V, RL = no load | 11 | |||
| Input offset voltage drift | dVOS/dT | 0.25 | µV/℃ | VCM = V–, TA = –40°C to 125°C | 9 | ||
| DC channel separation | 0.4 | µV/V | 9 | ||||
| Input bias current | IB | 10 | pA | 9 | |||
| Input offset current | IOS | 10 | pA | 9 | |||
| Input voltage noise, 0.1 Hz to 10 Hz (peak-to-peak) | EN | 2.7 | µVPP | f = 0.1 Hz to 10 Hz | 9 | ||
| Input voltage noise, 0.1 Hz to 10 Hz (RMS) | EN | 0.49 | µVRMS | f = 0.1 Hz to 10 Hz | 9 | ||
| Input voltage noise density | eN | 6.8 | nV/√Hz | f = 1 kHz | 9 | ||
| Input voltage noise density | eN | 4.2 | nV/√Hz | f = 10 kHz | 9 | ||
| Input current noise density | iN | 55 | fA/√Hz | f = 1 kHz | 9 | ||
| Common-mode rejection ratio (PMOS pair, VS = 2.7 V) | CMRR | 90 | dB | VS = 2.7 V, V– < VCM < (V+) – 2 V (PMOS pair) | 9 | ||
| Common-mode rejection ratio (NMOS pair) | CMRR | 78 | dB | VS = 2.7 – 16 V, (V+) – 1 V < VCM < V+ (NMOS pair) | 9 | ||
| Short-circuit current | ISC | 73 | mA | 11 | |||
| Gain-bandwidth product | GBW | 11 | MHz | 9 | |||
| Slew rate | SR | 33 | V/μs | VS = 16 V, G = +1, VSTEP = 10 V, CL = 20 pF | 9 | ||
| Phase margin | 64 | ° | G = +1, RL = 10 kΩ, CL = 20 pF | 10 | |||
| Overload recovery time | 120 | ns | VIN × gain > VS | 10 | |||
| Settling time to 0.1% | tS | 0.7 | μs | To 0.1%, VS = 16 V, VSTEP = 10 V, G = +1, CL = 20 pF | 10 | ||
| Settling time to 0.1% | tS | 0.22 | μs | To 0.1%, VS = 16 V, VSTEP = 2 V, G = +1, CL = 20 pF | 10 | ||
| Settling time to 0.01% | tS | 0.89 | μs | To 0.01%, VS = 16 V, VSTEP = 10 V, G = +1, CL = 20 pF | 10 | ||
| Settling time to 0.01% | tS | 0.42 | μs | To 0.01%, VS = 16 V, VSTEP = 2 V, G = +1, CL = 20 pF | 10 |
CAD (KiCad official)
- Symbol:
TLV9164IDR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
tlv9164idr-etched.step/tlv9164idr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tlv9164idr.step/tlv9164idr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (75 pp, sha256
55ab7b57bf9ad305, retrieved 2026-10-11, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).