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AIP74HC573SA20.TR
Public Made by Adomby adom
Wuxi I core Elec Signal Switches, Multiplexers, Decoders, SOP20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAIP74HC573SA20.TR
Wuxi I core Elec · Signal Switches, Multiplexers, Decoders · SOP20
AIP74HC573SA20.TR from Wuxi I core Elec, in a SOP20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OE | input | 3-state output enable input, active LOW; a HIGH on OE forces the Q outputs to the high-impedance OFF-state and does not change the latch contents. |
| 2 | D0 | input | Data input to latch 0; when LE is HIGH the latch is transparent and Q0 follows D0. |
| 3 | D1 | input | Data input to latch 1; when LE is HIGH the latch is transparent and Q1 follows D1. |
| 4 | D2 | input | Data input to latch 2; when LE is HIGH the latch is transparent and Q2 follows D2. |
| 5 | D3 | input | Data input to latch 3; when LE is HIGH the latch is transparent and Q3 follows D3. |
| 6 | D4 | input | Data input to latch 4; when LE is HIGH the latch is transparent and Q4 follows D4. |
| 7 | D5 | input | Data input to latch 5; when LE is HIGH the latch is transparent and Q5 follows D5. |
| 8 | D6 | input | Data input to latch 6; when LE is HIGH the latch is transparent and Q6 follows D6. |
| 9 | D7 | input | Data input to latch 7; when LE is HIGH the latch is transparent and Q7 follows D7. |
| 10 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 11 | LE | input | Latch enable input, active HIGH; the latches store the data present at the inputs on the HIGH-to-LOW transition of LE. |
| 12 | Q7 | tri_state | 3-state non-inverting latch output 7; goes to high-impedance when OE_ is HIGH. |
| 13 | Q6 | tri_state | 3-state non-inverting latch output 6; goes to high-impedance when OE_ is HIGH. |
| 14 | Q5 | tri_state | 3-state non-inverting latch output 5; goes to high-impedance when OE_ is HIGH. |
| 15 | Q4 | tri_state | 3-state non-inverting latch output 4; goes to high-impedance when OE_ is HIGH. |
| 16 | Q3 | tri_state | 3-state non-inverting latch output 3; goes to high-impedance when OE_ is HIGH. |
| 17 | Q2 | tri_state | 3-state non-inverting latch output 2; goes to high-impedance when OE_ is HIGH. |
| 18 | Q1 | tri_state | 3-state non-inverting latch output 1; goes to high-impedance when OE_ is HIGH. |
| 19 | Q0 | tri_state | 3-state non-inverting latch output 0; goes to high-impedance when OE_ is HIGH. |
| 20 | VCC | power_in | Supply voltage; 2.0 V to 6.0 V for the AiP74HC573 and 4.5 V to 5.5 V for the AiP74HCT573 per the recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Wuxi I core Elec |
| Package | SOP20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| supply voltage | VCC | -0.5 | 7 | V | 7 | ||
| input clamping current | IIK | -20 | 20 | mA | VI < -0.5V or VI > VCC+0.5V | 7 | |
| output clamping current | IOK | -20 | 20 | mA | VO < -0.5V or VO > VCC+0.5V | 7 | |
| output current | IO | -35 | 35 | mA | VO= -0.5V to (VCC+0.5V) | 7 | |
| supply current | ICC | 70 | mA | 7 | |||
| ground current | IGND | -70 | mA | 7 | |||
| storage temperature | Tstg | -65 | 150 | ℃ | 7 | ||
| total power dissipation | Ptot | 500 | mW | 7 | |||
| soldering temperature | TL | 250 | ℃ | 10s; SOP package | 7 | ||
| supply voltage | VCC | 2 | 5 | 6 | V | AiP74HC573 | 8 |
| input voltage | VI | 0 | V | AiP74HC573; max printed as VCC | 8 | ||
| output voltage | VO | 0 | V | AiP74HC573; max printed as VCC | 8 | ||
| input transition rise and fall rate | Δt/ΔV | 625 | ns/V | VCC=2.0V | 8 | ||
| input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC=4.5V | 8 | |
| input transition rise and fall rate | Δt/ΔV | 83 | ns/V | VCC=6.0V | 8 | ||
| ambient temperature | Tamb | -40 | 105 | ℃ | AiP74HC573 | 8 | |
| HIGH-level input voltage | VIH | 1.5 | V | Tamb=-40℃ to +105℃; VCC=2.0V | 10 | ||
| HIGH-level input voltage | VIH | 3.15 | V | Tamb=-40℃ to +105℃; VCC=4.5V | 10 | ||
| HIGH-level input voltage | VIH | 4.2 | V | Tamb=-40℃ to +105℃; VCC=6.0V | 10 | ||
| LOW-level input voltage | VIL | 0.5 | V | Tamb=-40℃ to +105℃; VCC=2.0V | 10 | ||
| LOW-level input voltage | VIL | 1.35 | V | Tamb=-40℃ to +105℃; VCC=4.5V | 10 | ||
| LOW-level input voltage | VIL | 1.8 | V | Tamb=-40℃ to +105℃; VCC=6.0V | 10 | ||
| HIGH-level output voltage | VOH | 1.9 | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=-20uA; VCC=2.0V | 10 | ||
| HIGH-level output voltage | VOH | 4.4 | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=-20uA; VCC=4.5V | 10 | ||
| HIGH-level output voltage | VOH | 5.9 | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=-20uA; VCC=6.0V | 10 | ||
| HIGH-level output voltage | VOH | 3.7 | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=-6.0mA; VCC=4.5V | 10 | ||
| HIGH-level output voltage | VOH | 5.2 | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=-7.8mA; VCC=6.0V | 10 | ||
| LOW-level output voltage | VOL | 0.1 | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=20uA; VCC=2.0V | 10 | ||
| LOW-level output voltage | VOL | 0.4 | V | Tamb=-40℃ to +105℃; VI = VIH or VIL; IO=6.0mA; VCC=4.5V | 10 | ||
| input leakage current | II | -1 | 1 | uA | Tamb=-40℃ to +105℃; VI=VCC or GND; VCC=6.0V | 10 | |
| OFF-state output current | IOZ | -10 | 10 | uA | Tamb=-40℃ to +105℃; VI=VIH or VIL; VCC=6.0V; VO=VCC or GND | 10 | |
| supply current | ICC | 160 | uA | Tamb=-40℃ to +105℃; VI=VCC or GND; IO=0A; VCC=6.0V | 11 | ||
| propagation delay Dn to Qn | tpd | 225 | ns | Tamb=-40℃ to +105℃; Dn to Qn; see Figure 6; VCC=2.0V | 14 | ||
| propagation delay Dn to Qn | tpd | 45 | ns | Tamb=-40℃ to +105℃; Dn to Qn; see Figure 6; VCC=4.5V | 14 | ||
| propagation delay Dn to Qn | tpd | 38 | ns | Tamb=-40℃ to +105℃; Dn to Qn; see Figure 6; VCC=6.0V | 14 | ||
| propagation delay LE to Qn | tpd | 225 | ns | Tamb=-40℃ to +105℃; LE to Qn; see Figure 7; VCC=2.0V | 14 | ||
| propagation delay LE to Qn | tpd | 45 | ns | Tamb=-40℃ to +105℃; LE to Qn; see Figure 7; VCC=4.5V | 14 | ||
| propagation delay LE to Qn | tpd | 38 | ns | Tamb=-40℃ to +105℃; LE to Qn; see Figure 7; VCC=6.0V | 14 | ||
| OE to Qn enable time | ten | 210 | ns | Tamb=-40℃ to +105℃; see Figure 8; VCC=2.0V | 14 | ||
| OE to Qn enable time | ten | 42 | ns | Tamb=-40℃ to +105℃; see Figure 8; VCC=4.5V | 14 | ||
| OE to Qn enable time | ten | 36 | ns | Tamb=-40℃ to +105℃; see Figure 8; VCC=6.0V | 14 | ||
| OE to Qn disable time | tdis | 225 | ns | Tamb=-40℃ to +105℃; see Figure 8; VCC=2.0V | 14 | ||
| OE to Qn disable time | tdis | 45 | ns | Tamb=-40℃ to +105℃; see Figure 8; VCC=4.5V | 14 | ||
| OE to Qn disable time | tdis | 38 | ns | Tamb=-40℃ to +105℃; see Figure 8; VCC=6.0V | 14 | ||
| transition time | tt | 90 | ns | Tamb=-40℃ to +105℃; Qn; see Figure 6; VCC=2.0V | 14 | ||
| transition time | tt | 18 | ns | Tamb=-40℃ to +105℃; Qn; see Figure 6; VCC=4.5V | 14 | ||
| transition time | tt | 15 | ns | Tamb=-40℃ to +105℃; Qn; see Figure 6; VCC=6.0V | 14 | ||
| pulse width LE HIGH | tW | 120 | ns | Tamb=-40℃ to +105℃; LE HIGH; see Figure 7; VCC=2.0V | 14 | ||
| pulse width LE HIGH | tW | 24 | ns | Tamb=-40℃ to +105℃; LE HIGH; see Figure 7; VCC=4.5V | 14 | ||
| pulse width LE HIGH | tW | 20 | ns | Tamb=-40℃ to +105℃; LE HIGH; see Figure 7; VCC=6.0V | 14 | ||
| set-up time Dn to LE | tsu | 75 | ns | Tamb=-40℃ to +105℃; Dn to LE; see Figure 9; VCC=2.0V | 14 | ||
| set-up time Dn to LE | tsu | 15 | ns | Tamb=-40℃ to +105℃; Dn to LE; see Figure 9; VCC=4.5V | 14 | ||
| set-up time Dn to LE | tsu | 13 | ns | Tamb=-40℃ to +105℃; Dn to LE; see Figure 9; VCC=6.0V | 14 | ||
| hold time Dn to LE | th | 5 | ns | Tamb=-40℃ to +105℃; Dn to LE; see Figure 9; VCC=2.0V | 14 |
CAD (KiCad official)
- Symbol:
AIP74HC573SA20.TR - Footprint:
Package_SO:SOP-20_7.5x12.8mm_P1.27mm - 3D model: SOP20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
aip74hc573sa20-tr-etched.step/aip74hc573sa20-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);aip74hc573sa20-tr.step/aip74hc573sa20-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Wuxi I core Elec datasheet (21 pp, sha256
26c3e753de4ac359, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).