component
MSP430FR5989IRGCT
Public Made by Adomby adom
Texas Instruments Microcontroller Units (MCUs/MPUs/SOCs), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430FR5989IRGCT
Texas Instruments · Microcontroller Units (MCUs/MPUs/SOCs) · VQFN-64-EP(9x9)
MSP430FR5989IRGCT from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P4.3/UCA0SOMI/UCA0RXD/UCB1STE | bidirectional | General-purpose digital I/O also providing USCI_A0 SPI slave-out/master-in and UART receive data, and USCI_B1 SPI slave transmit enable. |
| 2 | P1.4/UCB0CLK/UCA0STE/TA1.0 | bidirectional | General-purpose digital I/O also providing USCI_B0 SPI clock, USCI_A0 SPI slave transmit enable, and Timer_A TA1 CCR0 capture/compare output. |
| 3 | P1.5/UCB0STE/UCA0CLK/TA0.0 | bidirectional | General-purpose digital I/O also providing USCI_B0 SPI slave transmit enable, USCI_A0 SPI clock, and Timer_A TA0 CCR0 capture/compare output. |
| 4 | P1.6/UCB0SIMO/UCB0SDA/TA0.1 | bidirectional | General-purpose digital I/O also providing USCI_B0 SPI slave-in/master-out, I2C data, BSL data (I2C BSL devices), and Timer_A TA0 CCR1 capture/compare output. |
| 5 | P1.7/UCB0SOMI/UCB0SCL/TA0.2 | bidirectional | General-purpose digital I/O also providing USCI_B0 SPI slave-out/master-in, I2C clock, BSL clock (I2C BSL devices), and Timer_A TA0 CCR2 capture/compare output. |
| 6 | P2.4/TB0.3 | bidirectional | General-purpose digital I/O also providing Timer_B TB0 CCR3 capture/compare output. |
| 7 | P2.5/TB0.4 | bidirectional | General-purpose digital I/O also providing Timer_B TB0 CCR4 capture/compare output. |
| 8 | P2.6/TB0.5/ESIC1OUT | bidirectional | General-purpose digital I/O also providing Timer_B TB0 CCR5 capture/compare output and ESI Comparator 1 output. |
| 9 | P2.7/TB0.6/ESIC2OUT | bidirectional | General-purpose digital I/O also providing Timer_B TB0 CCR6 capture/compare output and ESI Comparator 2 output. |
| 10 | P5.0/TA1.1/MCLK | bidirectional | General-purpose digital I/O also providing Timer_A TA1 CCR1 capture/compare output and MCLK output. |
| 11 | P5.1/TA1.2 | bidirectional | General-purpose digital I/O also providing Timer_A TA1 CCR2 capture/compare output. |
| 12 | P5.2/TA1.0/TA1CLK/ACLK | bidirectional | General-purpose digital I/O also providing Timer_A TA1 CCR0 capture/compare output, Timer_A TA1 clock input, and ACLK output. |
| 13 | P5.3/UCB1STE | bidirectional | General-purpose digital I/O also providing USCI_B1 SPI slave transmit enable. |
| 14 | P3.0/UCB1CLK | bidirectional | General-purpose digital I/O also providing USCI_B1 SPI clock (slave-mode input or master-mode output). |
| 15 | P3.1/UCB1SIMO/UCB1SDA | bidirectional | General-purpose digital I/O also providing USCI_B1 SPI slave-in/master-out and I2C data. |
| 16 | P3.2/UCB1SOMI/UCB1SCL | bidirectional | General-purpose digital I/O also providing USCI_B1 SPI slave-out/master-in and I2C clock. |
| 17 | DVSS1 | power_in | Digital ground supply. |
| 18 | DVCC1 | power_in | Digital power supply; VCC is specified at 1.8 V to 3.6 V on all DVCC, AVCC and ESIDVCC pins, with 1 µF plus 100 nF decoupling recommended. |
| 19 | TEST/SBWTCK | input | Test mode pin used to select digital I/O on JTAG pins and as Spy-Bi-Wire input clock; it always has an internal pulldown enabled. |
| 20 | RST/NMI/SBWTDIO | bidirectional | Active-low reset input, nonmaskable interrupt input, and Spy-Bi-Wire data input/output. |
| 21 | PJ.0/TDO/TB0OUTH/SMCLK/SRSCG1 | bidirectional | General-purpose digital I/O also providing JTAG test data output, Timer_B TB0 PWM high-impedance switch input, SMCLK output, and low-power debug CPU status bit SCG1. |
| 22 | PJ.1/TDI/TCLK/MCLK/SRSCG0 | bidirectional | General-purpose digital I/O also providing JTAG test data input or test clock, MCLK output, and low-power debug CPU status bit SCG0. |
| 23 | PJ.2/TMS/ACLK/SROSCOFF | bidirectional | General-purpose digital I/O also providing JTAG test mode select, ACLK output, and low-power debug CPU status bit OSCOFF. |
| 24 | PJ.3/TCK/COUT/SRCPUOFF | bidirectional | General-purpose digital I/O also providing JTAG test clock, comparator output, and low-power debug CPU status bit CPUOFF. |
| 25 | P3.3/TA1.1/TB0CLK | bidirectional | General-purpose digital I/O also providing Timer_A TA1 CCR1 capture/compare output and Timer_B TB0 clock input. |
| 26 | P3.4/UCA1SIMO/UCA1TXD/TB0.0 | bidirectional | General-purpose digital I/O also providing USCI_A1 SPI slave-in/master-out, UART transmit data, and Timer_B TB0 CCR0 capture/compare output. |
| 27 | P3.5/UCA1SOMI/UCA1RXD/TB0.1 | bidirectional | General-purpose digital I/O also providing USCI_A1 SPI slave-out/master-in, UART receive data, and Timer_B TB0 CCR1 capture/compare output. |
| 28 | P3.6/UCA1CLK/TB0.2 | bidirectional | General-purpose digital I/O also providing USCI_A1 SPI clock and Timer_B TB0 CCR2 capture/compare output. |
| 29 | P3.7/UCA1STE/TB0.3 | bidirectional | General-purpose digital I/O also providing USCI_A1 SPI slave transmit enable and Timer_B TB0 CCR3 capture/compare output. |
| 30 | P2.3/UCA0STE/TB0OUTH | bidirectional | General-purpose digital I/O also providing USCI_A0 SPI slave transmit enable and Timer_B TB0 PWM high-impedance switch input. |
| 31 | P2.2/UCA0CLK/TB0.4/RTCCLK | bidirectional | General-purpose digital I/O also providing USCI_A0 SPI clock, Timer_B TB0 CCR4 capture/compare output, and RTC clock output for calibration. |
| 32 | P2.1/UCA0SOMI/UCA0RXD/TB0.5/DMAE0 | bidirectional | General-purpose digital I/O also providing USCI_A0 SPI slave-out/master-in, UART receive data, BSL receive (UART BSL devices), Timer_B TB0 CCR5 capture/compare output, and DMA external trigger input. |
| 33 | P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK | bidirectional | General-purpose digital I/O also providing USCI_A0 SPI slave-in/master-out, UART transmit data, BSL transmit (UART BSL devices), Timer_B TB0 CCR6 capture/compare output, and Timer_B TB0 clock input. |
| 34 | DVSS2 | power_in | Digital ground supply. |
| 35 | DVCC2 | power_in | Digital power supply; VCC is specified at 1.8 V to 3.6 V on all DVCC, AVCC and ESIDVCC pins. |
| 36 | P1.3/ESITEST4/TA1.2/A3/C3 | bidirectional | General-purpose digital I/O also providing ESI test signal 4, Timer_A TA1 CCR2 capture/compare output, analog input A3, and comparator input C3. |
| 37 | P1.2/TA1.1/TA0CLK/COUT/A2/C2 | bidirectional | General-purpose digital I/O also providing Timer_A TA1 CCR1 capture/compare output, Timer_A TA0 clock input, comparator output, analog input A2, and comparator input C2. |
| 38 | P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+ | bidirectional | General-purpose digital I/O also providing Timer_A TA0 CCR2 capture/compare output, Timer_A TA1 clock input, comparator output, analog input A1, comparator input C1, and positive reference voltage output or external positive reference input to the ADC. |
| 39 | P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF- | bidirectional | General-purpose digital I/O also providing Timer_A TA0 CCR1 capture/compare output, DMA external trigger input, RTC clock output for calibration, analog input A0, comparator input C0, and negative reference voltage output or external negative reference input to the ADC. |
| 40 | P9.0/ESICH0/ESITEST0/A8/C8 | bidirectional | General-purpose digital I/O also providing ESI channel 0 sensor excitation output and signal input, ESI test signal 0, analog input A8, and comparator input C8. |
| 41 | P9.1/ESICH1/ESITEST1/A9/C9 | bidirectional | General-purpose digital I/O also providing ESI channel 1 sensor excitation output and signal input, ESI test signal 1, analog input A9, and comparator input C9. |
| 42 | P9.2/ESICH2/ESITEST2/A10/C10 | bidirectional | General-purpose digital I/O also providing ESI channel 2 sensor excitation output and signal input, ESI test signal 2, analog input A10, and comparator input C10. |
| 43 | P9.3/ESICH3/ESITEST3/A11/C11 | bidirectional | General-purpose digital I/O also providing ESI channel 3 sensor excitation output and signal input, ESI test signal 3, analog input A11, and comparator input C11. |
| 44 | P9.4/ESICI0/A12/C12 | bidirectional | General-purpose digital I/O also providing ESI channel 0 signal input to comparator, analog input A12, and comparator input C12. |
| 45 | P9.5/ESICI1/A13/C13 | bidirectional | General-purpose digital I/O also providing ESI channel 1 signal input to comparator, analog input A13, and comparator input C13. |
| 46 | P9.6/ESICI2/A14/C14 | bidirectional | General-purpose digital I/O also providing ESI channel 2 signal input to comparator, analog input A14, and comparator input C14. |
| 47 | P9.7/ESICI3/A15/C15 | bidirectional | General-purpose digital I/O also providing ESI channel 3 signal input to comparator, analog input A15, and comparator input C15. |
| 48 | ESIDVCC | power_in | ESI power supply; TI recommends powering it from the same source as DVCC and AVCC, with 1 µF plus 100 nF decoupling. |
| 49 | ESIDVSS | power_in | ESI ground supply. |
| 50 | ESICI | input | ESI Scan IF input to the comparator; left open when unused. |
| 51 | ESICOM | passive | ESI common termination for Scan IF sensors; left open when unused. |
| 52 | AVCC1 | power_in | Analog power supply; VCC is specified at 1.8 V to 3.6 V on all AVCC, DVCC and ESIDVCC pins. |
| 53 | AVSS3 | power_in | Analog ground supply. |
| 54 | PJ.7/HFXOUT | bidirectional | General-purpose digital I/O also providing the output terminal of crystal oscillator XT2. |
| 55 | PJ.6/HFXIN | bidirectional | General-purpose digital I/O also providing the input terminal for crystal oscillator XT2. |
| 56 | AVSS1 | power_in | Analog ground supply. |
| 57 | PJ.4/LFXIN | bidirectional | General-purpose digital I/O also providing the input terminal for crystal oscillator XT1. |
| 58 | PJ.5/LFXOUT | bidirectional | General-purpose digital I/O also providing the output terminal of crystal oscillator XT1. |
| 59 | AVSS2 | power_in | Analog ground supply. |
| 60 | P4.0/UCB1SIMO/UCB1SDA/MCLK | bidirectional | General-purpose digital I/O also providing USCI_B1 SPI slave-in/master-out, I2C data, and MCLK output. |
| 61 | P4.1/UCB1SOMI/UCB1SCL/ACLK | bidirectional | General-purpose digital I/O also providing USCI_B1 SPI slave-out/master-in, I2C clock, and ACLK output. |
| 62 | DVSS3 | power_in | Digital ground supply. |
| 63 | DVCC3 | power_in | Digital power supply; VCC is specified at 1.8 V to 3.6 V on all DVCC, AVCC and ESIDVCC pins. |
| 64 | P4.2/UCA0SIMO/UCA0TXD/UCB1CLK | bidirectional | General-purpose digital I/O also providing USCI_A0 SPI slave-in/master-out, UART transmit data, and USCI_B1 SPI clock. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-64-EP(9x9) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 65 |
CAD (KiCad official)
- Symbol:
MSP430FR5989IRGCT - Footprint:
Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm - 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
- 3D model files:
msp430fr5989irgct-etched.step/msp430fr5989irgct-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430fr5989irgct.step/msp430fr5989irgct.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (190 pp, sha256
868055019a26de9e, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).