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CDCE62005RGZR

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Texas Instruments Clock Generators / Frequency Synthesizers / PLL, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentrtc-clock chipcdce62005rgzrfactory-2.0.0extractor-text

Verified CDCE62005RGZR

by Ray · last 2 Nov 2026 · 1 record · files match
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Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 49 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CDCE62005RGZR · VQFN-48-EP(7x7) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 86-page datasheet
  • ✓distributor: lcsc C2870969, digikey 296-38907-2-ND, mouser 595-CDCE62005RGZR
  • ✓family: QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-1x604pyu/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cdce62005rgzr.kicad_sym✓ cdce62005rgzr.kicad_mod✓ cdce62005rgzr.step
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Contents

README

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CDCE62005RGZR

Texas Instruments · Clock Generators / Frequency Synthesizers / PLL · VQFN-48-EP(7x7)

CDCE62005RGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC_IN_SEC power_in 3.3-V supply for the secondary reference input buffer and circuitry.
2 SEC_REF- input Universal input buffer (LVPECL, LVDS) negative input for the secondary reference clock; for LVCMOS input on SEC_REF+, connect through 1-kΩ resistor to GND.
3 SEC_REF+ input Universal input buffer (LVPECL, LVDS, LVCMOS) positive input for the secondary reference clock.
4 REG_CAP1 passive Capacitor connection for the internal regulator; connect to a 10-µF capacitor (X5R or X7R).
5 VCC1_PLL power_in 3.3-V PLL supply voltage for the PLL circuitry (filter required).
6 U4P output Main output 4 positive; user-definable as LVPECL, LVDS or LVCMOS.
7 U4N output Main output 4 negative; user-definable as LVPECL, LVDS or LVCMOS.
8 VCC_OUT power_in 3.3-V supply for the output buffers and output dividers.
9 U3P output Main output 3 positive; user-definable as LVPECL, LVDS or LVCMOS.
10 U3N output Main output 3 negative; user-definable as LVPECL, LVDS or LVCMOS.
11 VCC_OUT power_in 3.3-V supply for the output buffers and output dividers.
12 Power_Down input Active-low power-down input with internal 150-kΩ pull-up; SPI_LE must be high for the rising edge to load the EEPROM.
13 AUX OUT output Auxiliary LVCMOS-level output programmable via SPI to be driven by Output 2 or Output 3.
14 SYNC input Active-low sync mode input with internal 150-kΩ pull-up.
15 VCC_AUXOUT power_in 3.3-V supply to power the AUX_OUT circuitry.
16 U2P output Main output 2 positive; user-definable as LVPECL, LVDS or LVCMOS.
17 U2N output Main output 2 negative; user-definable as LVPECL, LVDS or LVCMOS.
18 VCC_OUT power_in 3.3-V supply for the output buffers and output dividers.
19 U1P output Main output 1 positive; user-definable as LVPECL, LVDS or LVCMOS.
20 U1N output Main output 1 negative; user-definable as LVPECL, LVDS or LVCMOS.
21 VCC_OUT power_in 3.3-V supply for the output buffers and output dividers.
22 SPI_MISO tri_state 3-state LVCMOS serial data output to the SPI bus, enabled when SPI_LE is asserted low.
23 SPI_MOSI input LVCMOS serial control data input for the SPI bus with internal 150-kΩ pull-up.
24 SPI_CLK input LVCMOS serial control clock input for the SPI bus with hysteresis and internal 150-kΩ pull-up.
25 SPI_LE input LVCMOS latch enable input for the SPI with hysteresis and internal 150-kΩ pull-up; it must be logic 1 before Power_Down toggles low-to-high for EEPROM load.
26 VCC_OUT power_in 3.3-V supply for the output buffers and output dividers.
27 U0P output Main output 0 positive; user-definable as LVPECL, LVDS or LVCMOS.
28 U0N output Main output 0 negative; user-definable as LVPECL, LVDS or LVCMOS.
29 VCC_OUT power_in 3.3-V supply for the output buffers and output dividers.
30 TESTOUTA passive Reserved analog pin; pull down to GND via a 1-kΩ resistor.
31 REF_SEL input External input reference select with internal 150-kΩ pull-up, active only when auto reference select mode is off.
32 VCC_OUT power_in 3.3-V supply for the output buffers and output dividers.
33 TEST_MODE input Should be tied high or left unconnected.
34 VCC_VCO power_in 3.3-V VCO input buffer and circuitry supply voltage (filter required).
35 VCC_VCO power_in 3.3-V VCO input buffer and circuitry supply voltage (filter required).
36 GND_VCO power_in Ground connection to VCO ground, shorted to GND.
37 PLL_LOCK output Output indicating PLL lock status.
38 REG_CAP2 passive Capacitor connection for the internal regulator; connect to a 10-µF capacitor (X5R or X7R).
39 VCC2_PLL power_in 3.3-V PLL supply voltage for the PLL circuitry (filter required).
40 EXT_LFP passive External loop filter input, positive.
41 EXT_LFN passive External loop filter input, negative.
42 VCC2_PLL power_in 3.3-V PLL supply voltage for the PLL circuitry (filter required).
43 AUX IN input Single-ended auxiliary input with on-board oscillator circuit so a crystal may be connected.
44 VCC_AUXIN power_in 3.3-V supply for the crystal oscillator input circuitry.
45 PRI_REF+ input Universal input buffer (LVPECL, LVDS, LVCMOS) positive input for the primary reference clock.
46 PRI_REF- input Universal input buffer (LVPECL, LVDS) negative input for the primary reference clock; for LVCMOS input on PRI_REF+, connect through 1-kΩ resistor to GND.
47 VCC_IN_PRI power_in 3.3-V supply for the primary reference input buffer and circuitry.
48 VBB passive Capacitor connection for the internal termination voltage; connect to a 1-µF capacitor (X5R or X7R).
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category RTC/Clock Chip
Pins 49

CAD (KiCad official)

  • Symbol: CDCE62005RGZR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: cdce62005rgzr-etched.step / cdce62005rgzr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cdce62005rgzr.step / cdce62005rgzr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (86 pp, sha256 d29c55d80466bf88, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF