LT3844EFE#PBF from Analog Devices, in a TSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VIN	power_in	VIN is the main supply pin with an operating voltage range of 4V to 60V and should be decoupled to SGND with a low ESR capacitor located close to the pin.
2	SHDN	input	SHDN has a precision enable threshold of 1.35V (rising) with 120mV of hysteresis, pulling it below a transistor VBE (0.7V) enters shutdown, and the pin is internally clamped to 6V with typical input bias current below 10µA.
3	CSS	passive	CSS programs the soft-start function using CSS = 2µA(tSS/1.231V) for a given output voltage slew rate, and should be left unconnected when soft-start is not used.
4	BURST_EN	input	BURST_EN must be connected to ground to enable Burst Mode operation and connected to VFB or VCC to disable it.
5	VFB	input	VFB is the output voltage feedback input, connected to the supply output through a resistive divider, feeds the inverting input of the error amplifier, and regulates at 1.231V.
6	VC	passive	VC is the error amplifier output (peak switch current command) that is typically compensated with an RC network to SGND, is clamped 100mV below the burst threshold when Burst Mode is enabled, cannot be pulled low by a low impedance source, and should be driven through a 1k series resistance if externally manipulated.
7	SYNC	input	SYNC is the external clock input for oscillator synchronization, with RSET set so the internal oscillator runs 10% to 25% below the external clock frequency, and should be connected to SGND if unused.
8	fSET	passive	fSET programs the oscillator frequency with an external resistor RSET, which is required even when an external sync clock is supplied.
9	SGND	power_in	SGND is the low noise ground reference that should be connected to the -VOUT side of the output capacitors, with high currents kept away from this connection.
10	SENSE-	input	SENSE- is the negative input of the current sense amplifier, connected to the VOUT side of the sense resistor in step-down applications, with the sensed inductor current limit set to 100mV across the SENSE inputs.
11	SENSE+	input	SENSE+ is the positive input of the current sense amplifier, connected to the inductor side of the sense resistor in step-down applications, with the sensed inductor current limit set to 100mV across the SENSE inputs.
12	PGND	power_in	PGND is the high current ground reference for the internal low side switch and VCC regulator and must be connected directly to the negative terminal of the VCC decoupling capacitor.
13	VCC	power_out	VCC is the internal bias supply decoupling node that requires a low ESR 1µF or greater ceramic capacitor to PGND, may be back-driven from an external DC source to improve efficiency, and sinks 20µA in shutdown until discharged to 0V.
14	SW	passive	SW is connected to the cathode of the external clamping Schottky diode, the power MOSFET drain and the inductor, and swings from VIN during the on-time to a Schottky voltage drop below ground during the off-time.
15	TG	output	TG is the bootstrapped gate drive for the top N-Channel MOSFET and should be connected to the MOSFET gate with a short and wide PCB trace to minimize inductance.
16	BOOST	power_in	BOOST supplies the bootstrapped gate drive, is referenced to SW through a low ESR ceramic boost capacitor (recommended 50 times the top MOSFET total input capacitance, 0.1µF adequate in most applications), and sees a maximum of VIN + VCC ground referred.
17	SGND (Exposed Pad)	power_in	The exposed pad is internally connected to SGND and must be soldered to the PCB ground for electrical contact and optimal thermal performance.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-16-EP
Category	Power Management ICs
Pins	17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VIN Operating Voltage Range		4		60	V		2
VIN UVLO Threshold (Falling)		3.6	3.8	4	V		2
VIN Shutdown Current			10	15	µA	VSHDN = 0V	2
SHDN Enable Threshold (Rising)		1.3	1.35	1.4	V		3
Error Amp Reference Voltage (VFB pin)		1.224	1.231	1.238	V		3
Error Amp Reference Voltage (VFB pin, full operating temperature range)		1.215		1.245	V	Over full operating temperature range	3
Sense Pins Common Mode Range		0		36	V		3
Current Limit Sense Voltage (VSENSE+, VSENSE-)		90	100	115	mV	Over full operating temperature range	3
VCC Supply Current			1.7	2.1	mA		3
Operating Frequency		290	300	310	kHz		3
Operating Frequency (full operating temperature range)		270		330	kHz	Over full operating temperature range	3
Minimum Programmable Frequency		100			kHz		3
Maximum Programmable Frequency				500	kHz		3
External Sync Frequency Range		100		600	kHz		3
SYNC Voltage Threshold		1.4		2	V		3
Error Amp Transconductance	gm	270	340	410	µS	Over full operating temperature range	3
Error Amp Sink/Source Current		-30		30	µA		3
TG Drive On Voltage		9.8			V	CLOAD = 2200pF	3
TG Drive Off Voltage				0.1	V	CLOAD = 2200pF	3
Minimum TG Off Time		350		500	ns	Over full operating temperature range	3
Minimum TG On Time		250		350	ns	Over full operating temperature range	3
Input Supply Voltage (VIN)	VIN	-0.3		65	V		2
Boosted Supply Voltage (BOOST)	BOOST	-0.3		80	V		2
Switch Voltage (SW)	SW	-1		65	V	Note 8	2
Differential Boost Voltage (BOOST to SW)		-0.3		24	V		2
Bias Supply Voltage (VCC)	VCC	-0.3		24	V		2
SENSE+ and SENSE- Voltages		-0.3		40	V		2
Differential Sense Voltage (SENSE+ to SENSE-)		-1		1	V		2
BURST_EN Voltage		-0.3		24	V		2
SYNC, VC, VFB, CSS and SHDN Voltages		-0.3		5	V		2
SHDN Pin Current				1	mA		2
Operating Junction Temperature Range (LT3844E)	TJ	-40		125	°C	Note 3	2
Storage Temperature	TSTG	-65		150	°C		2
Lead Temperature (Soldering, 10 sec)				300	°C	10 sec soldering	2
Maximum Junction Temperature	TJMAX			125	°C		2
Junction-to-Ambient Thermal Resistance	θJA		40		°C/W		2
Junction-to-Case Thermal Resistance	θJC		10		°C/W		2

CAD (KiCad official)

Symbol: LT3844EFE#PBF
Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
3D model: TSSOP-16-EP (KiCad packages3D, STEP)
3D model files: lt3844efe-pbf-etched.step / lt3844efe-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lt3844efe-pbf.step / lt3844efe-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (26 pp, sha256 ce6947436197972c, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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LT3844EFE#PBF

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