LAN9514I-JZX from Microchip Tech, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	USBDM2	bidirectional	Downstream USB peripheral 2 DMINUS signal; all required USB series termination and pull-up/pull-down resistors are integrated into the hub.
2	USBDP2	bidirectional	Downstream USB peripheral 2 DPLUS signal; all required USB series termination and pull-up/pull-down resistors are integrated into the hub.
3	USBDM3	bidirectional	Downstream USB peripheral 3 DMINUS signal; all required USB series termination and pull-up/pull-down resistors are integrated into the hub.
4	USBDP3	bidirectional	Downstream USB peripheral 3 DPLUS signal; all required USB series termination and pull-up/pull-down resistors are integrated into the hub.
5	VDD33A	power_in	+3.3V analog power supply; refer to the reference schematics for connection information.
6	USBDM4	bidirectional	Downstream USB peripheral 4 DMINUS signal; all required USB series termination and pull-up/pull-down resistors are integrated into the hub.
7	USBDP4	bidirectional	Downstream USB peripheral 4 DPLUS signal; all required USB series termination and pull-up/pull-down resistors are integrated into the hub.
8	USBDM5	bidirectional	Downstream USB peripheral 5 DMINUS signal; all required USB series termination and pull-up/pull-down resistors are integrated into the hub.
9	USBDP5	bidirectional	Downstream USB peripheral 5 DPLUS signal; all required USB series termination and pull-up/pull-down resistors are integrated into the hub.
10	VDD33A	power_in	+3.3V analog power supply; refer to the reference schematics for connection information.
11	VBUS_DET	input	5 V-tolerant Schmitt input that detects upstream bus power; the hub uses it to decide when to assert the USBDP0 pull-up, and it must be tied to VDD33IO for bus-powered hubs.
12	nRESET	input	Active-low input allowing external hardware to reset the device; it should be tied high if not used.
13	TEST1	unconnected	Factory test pin; it must always be left unconnected.
14	PRTCTL2	bidirectional	Port power control for downstream peripheral 2: as output it enables port power, as input it senses an external current monitor where a low indicates overcurrent (IS/OD12 with internal pull-up).
15	VDD18CORE	power_out	+1.8V output from the internal core voltage regulator; all VDD18CORE pins must be tied together for proper operation.
16	PRTCTL3	bidirectional	Port power control for downstream peripheral 3: as output it enables port power, as input it senses an external current monitor where a low indicates overcurrent (IS/OD12 with internal pull-up).
17	PRTCTL4	bidirectional	Port power control for downstream peripheral 4: as output it enables port power, as input it senses an external current monitor where a low indicates overcurrent (IS/OD12 with internal pull-up).
18	PRTCTL5	bidirectional	Port power control for downstream peripheral 5: as output it enables port power, as input it senses an external current monitor where a low indicates overcurrent (IS/OD12 with internal pull-up).
19	VDD33IO	power_in	+3.3V power supply for I/O pins; refer to the reference schematics for connection information.
20	nFDX_LED/GPIO0	bidirectional	Ethernet full-duplex LED output, driven low when the link is full-duplex; also General Purpose I/O 0, programmable as push-pull output, open-drain output, or Schmitt-triggered input.
21	nLNKA_LED/GPIO1	bidirectional	Ethernet link/activity LED, driven low on a valid link and pulsed high for 80 ms on TX/RX activity; also General Purpose I/O 1, programmable as push-pull, open-drain, or Schmitt-triggered input.
22	nSPD_LED/GPIO2	bidirectional	Ethernet speed LED, driven low at 100 Mbps or during auto-negotiation; also General Purpose I/O 2, programmable as push-pull, open-drain, or Schmitt-triggered input.
23	EECLK	output	EEPROM clock output (O8) driving the clock of the external EEPROM.
24	EECS	output	EEPROM chip select output (O8) driving the chip select of the external EEPROM.
25	EEDO	output	EEPROM data output (O8) driving the EEDI input of the external EEPROM.
26	EEDI	input	EEPROM data input (IS, pull-down) driven by the EEDO output of the external EEPROM.
27	VDD33IO	power_in	+3.3V power supply for I/O pins; refer to the reference schematics for connection information.
28	nTRST	input	Active-low JTAG test port reset input; it should be tied high if not used.
29	TMS	input	JTAG test mode select input.
30	TDI	input	JTAG test data input.
31	TDO	output	JTAG test data output (O12).
32	TCK	input	JTAG test clock input; it should be tied high through a 10 kΩ resistor.
33	VDD33IO	power_in	+3.3V power supply for I/O pins; refer to the reference schematics for connection information.
34	TEST2	passive	Factory test pin; it must always be connected to VSS for proper operation.
35	GPIO3	bidirectional	General Purpose I/O 3 (IS/O8/OD8, pull-up), programmable as push-pull output, open-drain output, or Schmitt-triggered input.
36	GPIO4	bidirectional	General Purpose I/O 4 (IS/O8/OD8, pull-up), programmable as push-pull output, open-drain output, or Schmitt-triggered input.
37	GPIO5	bidirectional	General Purpose I/O 5 (IS/O8/OD8, pull-up), programmable as push-pull output, open-drain output, or Schmitt-triggered input.
38	VDD18CORE	power_out	+1.8V output from the internal core voltage regulator; all VDD18CORE pins must be tied together for proper operation.
39	VDD33IO	power_in	+3.3V power supply for I/O pins; refer to the reference schematics for connection information.
40	TEST3	passive	Factory test pin; it must always be connected to VDD33IO for proper operation.
41	AUTOMDIX_EN	input	Sets the default Auto-MDIX setting: 0 = Auto-MDIX disabled, 1 = Auto-MDIX enabled.
42	GPIO6	bidirectional	General Purpose I/O 6 (IS/O8/OD8, pull-up), programmable as push-pull output, open-drain output, or Schmitt-triggered input.
43	GPIO7	bidirectional	General Purpose I/O 7 (IS/O8/OD8, pull-up), programmable as push-pull output, open-drain output, or Schmitt-triggered input.
44	CLK24_EN	input	Enables generation of the 24 MHz clock on the CLK24_OUT pin.
45	CLK24_OUT	output	Outputs a 24 MHz clock (O8) that can be used as a reference clock for a partner hub.
46	VDD33IO	power_in	+3.3V power supply for I/O pins; refer to the reference schematics for connection information.
47	TEST4	unconnected	Factory test pin; it must always be left unconnected.
48	VDD18ETHPLL	power_in	+1.8V power supply for the Ethernet PLL; refer to the reference schematics for connection information.
49	VDD33A	power_in	+3.3V analog power supply; refer to the reference schematics for connection information.
50	EXRES	passive	External PHY bias resistor pin; connect to an external 12.4K 1.0% resistor to ground for the internal bias circuits.
51	VDD33A	power_in	+3.3V analog power supply; refer to the reference schematics for connection information.
52	RXP	bidirectional	Positive input of the Ethernet receiver; its receive inputs may be swapped internally with the transmit outputs when Auto-MDIX is enabled.
53	RXN	bidirectional	Negative input of the Ethernet receiver; its receive inputs may be swapped internally with the transmit outputs when Auto-MDIX is enabled.
54	VDD33A	power_in	+3.3V analog power supply; refer to the reference schematics for connection information.
55	TXP	bidirectional	Positive output of the Ethernet transmitter; its transmit outputs may be swapped internally with the receive inputs when Auto-MDIX is enabled.
56	TXN	bidirectional	Negative output of the Ethernet transmitter; its transmit outputs may be swapped internally with the receive inputs when Auto-MDIX is enabled.
57	VDD33A	power_in	+3.3V analog power supply; refer to the reference schematics for connection information.
58	USBDM0	bidirectional	Upstream USB DMINUS signal.
59	USBDP0	bidirectional	Upstream USB DPLUS signal; the hub asserts its internal pull-up on this pin to signal a connect event, based on VBUS_DET.
60	XO	output	External 25 MHz crystal output (OCLK); must be left unconnected if XI is driven by a single-ended clock oscillator.
61	XI	input	External 25 MHz crystal input (ICLK); it can also be driven by a single-ended clock oscillator, in which case XO is left unconnected.
62	VDD18USBPLL	power_in	+1.8V power supply for the USB PLL; refer to the reference schematics for connection information.
63	USBRBIAS	passive	External USB bias resistor pin; connect to an external 12K 1.0% resistor to ground to set HS transmit current and on-chip termination impedance.
64	VDD33A	power_in	+3.3V analog power supply; refer to the reference schematics for connection information.
65	VSS	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-64-EP(9x9)
Category	Interface ICs
Pins	65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage (absolute maximum)	VDD33IO, VDD33A	0		3.6	V	Note 4-1	38
Positive voltage on signal pins				6	V	w.r.t. ground; does not apply to XI, XO, EXRES, USBRBIAS (Note 4-2)	38
Negative voltage on signal pins		-0.5			V	w.r.t. ground; does not apply to EXRES, USBRBIAS (Note 4-3)	38
Positive voltage on XI				4.6	V	w.r.t. ground	38
Positive voltage on XO				2.5	V	w.r.t. ground	38
Ambient operating temperature in still air (industrial)	TA	-40		85	°C	Industrial version (LAN9514I); commercial is 0 to +70 °C (Note 4-4)	38
Storage temperature		-55		150	°C		38
HBM ESD performance		-8		8	kV	per JESD 22-A114-E	38
Contact discharge ESD performance		-8		8	kV	per IEC61000-4-2 (Note 4-5)	38
Air-gap discharge ESD performance		-15		15	kV	per IEC61000-4-2 (Note 4-5)	38
Latch-up performance		-200		200	mA	per EIA/JESD 78	38
Supply voltage tolerance	VDD33A, VDD33BIAS, VDD33IO	-300		300	mV	around +3.3 V nominal	38
Negative-going threshold (IS input, VILT)	VILT	1.01	1.18	1.35	V	Note 4-6	41
Positive-going threshold (IS input, VIHT)	VIHT	1.39	1.6	1.8	V	Note 4-6	41
Schmitt trigger hysteresis (IS input, VIHT - VILT)	VHYS	345	420	485	mV	Note 4-6	41
Input leakage (IS input)	IIH	-10		10	μA	VIN = VSS or VDD33IO	41
Input leakage (IS_5V input)	IIH	-10		10	μA	VIN = VSS or VDD33IO	41
Input leakage (IS_5V input at 5.5 V)	IIH			120	μA	VIN = 5.5V; total for entire device (Note 4-7)	41
Low output level (O8 buffer)	VOL			0.4	V	IOL = 8mA	41
Low output level (OD8 buffer)	VOL			0.4	V	IOL = 8mA	41
Low output level (O12 buffer)	VOL			0.4	V	IOL = 12mA	41
Low output level (OD12 buffer)	VOL			0.4	V	IOL = 12mA	41
Peak differential output voltage high (100BASE-TX)	VPPH	950		1050	mVpk	line side of transformer, line replaced by 100Ω ±1% (Note 4-9)	42
Peak differential output voltage low (100BASE-TX)	VPPL	-950		-1050	mVpk	line side of transformer (Note 4-9); printed as -950 / -1050	42
Signal amplitude symmetry	VSS	98		102	%	Note 4-9	42
Signal rise and fall time	TRF	3		5	nS	Note 4-9	42
Rise and fall symmetry	TRFS			0.5	nS	Note 4-9	42
Duty cycle distortion	DCD	35	50	65	%	Note 4-10	42
Overshoot and undershoot	VOS			5	%		42
Jitter				1.4	nS	measured differentially (Note 4-11)	42
Transmitter peak differential output voltage (10BASE-T)	VOUT	2.2	2.5	2.8	V	100 Ω resistive load (Note 4-12)	42
Receiver differential squelch threshold (10BASE-T)	VDS	300	420	585	mV		42
Frequency tolerance at 25°C (crystal)	Ftol	-50		50	PPM	25°C; Note 4-13	45
Frequency stability over temperature (crystal)	Ftemp	-50		50	PPM	over temperature; Note 4-13	45
Total allowable PPM budget (crystal)		-50		50	PPM	IEEE 802.3u; Note 4-15	45
Drive level (crystal)	PW	300			uW		45
Equivalent series resistance (crystal)	R1			50	Ω		45
Input clock duty cycle		40	50	60	%	single-ended clock oscillator on XI (Section 4.6)	45
nRESET input assertion time		1			μS	minimum assertion period (Section 4.5.2)	43
TCK clock period	ttckp	66.67			ns		45
TDI, TMS setup to TCK rising edge	tsu	10			ns		45
TDI, TMS hold from TCK rising edge	th	10			ns		45
TDO output valid from TCK falling edge	tdov			16	ns		45
TDO output hold from TCK falling edge	tdoh	0			ns		45
EECLK cycle time	tckcyc	1110		1130	ns		44
EECLK high time	tckh	550		570	ns		44
EECLK low time	tckl	550		570	ns		44
EECS high before rising edge of EECLK	tcshckh	1070			ns		44
EECLK falling edge to EECS low	tcklcsl	30			ns		44
EEDO valid before rising edge of EECLK	tdvckh	550			ns		44
EEDO disable after rising edge EECLK	tckhdis	550			ns		44
EEDI setup to rising edge of EECLK	tdsckh	90			ns		44
EEDI hold after rising edge of EECLK	tdhckh	0			ns		44
EECLK low to data disable (OUTPUT)	tckldis	580			ns		44
EEDIO valid after EECS high (VERIFY)	tcshdv			600	ns		44
EEDIO hold after EECS low (VERIFY)	tdhcsl	0			ns		44
EECS low	tcsl	1070			ns		44
Supply voltage (nominal)	VDD33A, VDD33BIAS, VDD33IO		3.3		V	+3.3 V ±300 mV tolerance given in separate row	38

CAD (KiCad official)

Symbol: LAN9514I-JZX
Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
3D model files: lan9514i-jzx-etched.step / lan9514i-jzx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lan9514i-jzx.step / lan9514i-jzx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (54 pp, sha256 257be1d7c91fac08, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

LAN9514I-JZX

Verified LAN9514I-JZX

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README