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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

ADS8588SIPMR

Texas Instruments · Analog To Digital Converters (ADC) · LQFP-64(10x10)

ADS8588SIPMR from Texas Instruments, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVDD	power_in	Analog supply pin (4.75 V to 5.25 V); decouple to AGND with 1-µF capacitor.
2	AGND	power_in	Analog ground pin; connect to common ground plane.
3	OS0	input	Oversampling mode control pin (LSB of OS[2:0]).
4	OS1	input	Oversampling mode control pin (middle bit of OS[2:0]).
5	OS2	input	Oversampling mode control pin (MSB of OS[2:0]).
6	PAR/SER/BYTE SEL	input	Logic input to select parallel (low), serial (high with DB15/BYTE SEL=low), or parallel byte (high with DB15/BYTE SEL=high) interface mode.
7	STBY	input	Active low logic input to enter standby or shutdown power-down mode depending on RANGE pin.
8	RANGE	input	Multi-function: when STBY=high selects ±10 V (high) or ±5 V (low) input range; when STBY=low selects standby (high) or shutdown (low) mode.
9	CONVSTA	input	Active high logic input to initiate simultaneous sampling of first half channels (1-4).
10	CONVSTB	input	Active high logic input to initiate simultaneous sampling of second half channels (5-8).
11	RESET	input	Active high logic input to reset device digital logic; minimum pulse width 50 ns.
12	RD/SCLK	input	Active low read enable in parallel modes, or serial clock input in serial mode.
13	CS	input	Active low chip-select signal; controls output driver tri-state mode.
14	BUSY	output	Active high digital output indicating analog-to-digital conversion in progress.
15	FRSTDATA	tri_state	Active high tri-state output indicating conversion data from channel 1 is being read.
16	DB0	tri_state	Tri-state data output bit 0 (LSB) in parallel modes when CS and RD both low.
17	DB1	tri_state	Tri-state data output bit 1 in parallel modes when CS and RD both low.
18	DB2	tri_state	Tri-state data output bit 2 in parallel modes when CS and RD both low.
19	DB3	tri_state	Tri-state data output bit 3 in parallel modes when CS and RD both low.
20	DB4	tri_state	Tri-state data output bit 4 in parallel modes when CS and RD both low.
21	DB5	tri_state	Tri-state data output bit 5 in parallel modes when CS and RD both low.
22	DB6	tri_state	Tri-state data output bit 6 in parallel modes when CS and RD both low.
23	DVDD	power_in	Digital supply pin (2.3 V to 5.25 V); decouple to digital ground with 1-µF capacitor minimum.
24	DB7/DOUTA	tri_state	Multi-function tri-state output: data bit 7 in parallel mode, or first serial output in serial mode.
25	DB8/DOUTB	tri_state	Multi-function tri-state output: data bit 8 in parallel mode, or second serial output in serial mode.
26	AGND	power_in	Analog ground pin; connect to common ground plane.
27	DB9	tri_state	Tri-state data output bit 9 in parallel modes when CS and RD both low.
28	DB10	tri_state	Tri-state data output bit 10 in parallel modes when CS and RD both low.
29	DB11	tri_state	Tri-state data output bit 11 in parallel modes when CS and RD both low.
30	DB12	tri_state	Tri-state data output bit 12 in parallel modes when CS and RD both low.
31	DB13	tri_state	Tri-state data output bit 13 in parallel modes when CS and RD both low.
32	DB14/HBEN	bidirectional	Tri-state data output bit 14 in parallel mode, or byte order select control in parallel byte mode.
33	DB15/BYTE SEL	bidirectional	Tri-state data output bit 15 (MSB) in parallel mode, or interface mode select control in non-parallel modes.
34	REFSEL	input	Active high logic input; selects internal 2.5-V reference (high) or external reference input (low).
35	AGND	power_in	Analog ground pin; connect to common ground plane.
36	REGCAP1	output	Internal voltage regulator output pin; decouple separately to AGND with 1-µF capacitor.
37	AVDD	power_in	Analog supply pin (4.75 V to 5.25 V); decouple to AGND with 1-µF capacitor.
38	AVDD	power_in	Analog supply pin (4.75 V to 5.25 V); decouple to AGND with 1-µF capacitor.
39	REGCAP2	output	Internal voltage regulator output pin; decouple separately to AGND with 1-µF capacitor.
40	AGND	power_in	Analog ground pin; connect to common ground plane.
41	AGND	power_in	Analog ground pin; connect to common ground plane.
42	REFIN/REFOUT	bidirectional	Internal 2.5-V reference output (REFSEL=high) or external reference input 2.475-2.525 V (REFSEL=low); decouple with 10-µF capacitor.
43	REFGND	power_in	Reference ground pin; connect to analog ground plane and decouple REFIN/REFOUT with 10-µF capacitor.
44	REFCAPA	output	Reference buffer output pin; externally short to REFCAPB and decouple to AGND with 10-µF capacitor.
45	REFCAPB	output	Reference buffer output pin; externally short to REFCAPA and decouple to AGND with 10-µF capacitor.
46	REFGND	power_in	Reference ground pin; connect to analog ground plane and decouple REFIN/REFOUT with 10-µF capacitor.
47	AGND	power_in	Analog ground pin; connect to common ground plane.
48	AVDD	power_in	Analog supply pin (4.75 V to 5.25 V); decouple to AGND with 1-µF capacitor.
49	AIN_1P	input	Channel 1 positive analog input; 1 MΩ impedance; accepts ±10 V or ±5 V depending on RANGE pin.
50	AIN_1GND	input	Channel 1 negative analog input; may be offset from AGND by ±0.3 V.
51	AIN_2P	input	Channel 2 positive analog input; 1 MΩ impedance; accepts ±10 V or ±5 V depending on RANGE pin.
52	AIN_2GND	input	Channel 2 negative analog input; may be offset from AGND by ±0.3 V.
53	AIN_3P	input	Channel 3 positive analog input; 1 MΩ impedance; accepts ±10 V or ±5 V depending on RANGE pin.
54	AIN_3GND	input	Channel 3 negative analog input; may be offset from AGND by ±0.3 V.
55	AIN_4P	input	Channel 4 positive analog input; 1 MΩ impedance; accepts ±10 V or ±5 V depending on RANGE pin.
56	AIN_4GND	input	Channel 4 negative analog input; may be offset from AGND by ±0.3 V.
57	AIN_5P	input	Channel 5 positive analog input; 1 MΩ impedance; accepts ±10 V or ±5 V depending on RANGE pin.
58	AIN_5GND	input	Channel 5 negative analog input; may be offset from AGND by ±0.3 V.
59	AIN_6P	input	Channel 6 positive analog input; 1 MΩ impedance; accepts ±10 V or ±5 V depending on RANGE pin.
60	AIN_6GND	input	Channel 6 negative analog input; may be offset from AGND by ±0.3 V.
61	AIN_7P	input	Channel 7 positive analog input; 1 MΩ impedance; accepts ±10 V or ±5 V depending on RANGE pin.
62	AIN_7GND	input	Channel 7 negative analog input; may be offset from AGND by ±0.3 V.
63	AIN_8P	input	Channel 8 positive analog input; 1 MΩ impedance; accepts ±10 V or ±5 V depending on RANGE pin.
64	AIN_8GND	input	Channel 8 negative analog input; may be offset from AGND by ±0.3 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	LQFP-64(10x10)
Category	Data Acquisition
Pins	64

CAD (KiCad official)

Symbol: ADS8588SIPMR
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ads8588sipmr-etched.step / ads8588sipmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads8588sipmr.step / ads8588sipmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (62 pp, sha256 a5e54af2bcb72584, retrieved 2026-09-26, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF