C8051F330-GM from SILICON LABS, in a QFN-20-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P0.0/VREF	bidirectional	Port 0.0 digital I/O or analog input, or external VREF input.
2	GND	power_in	Ground.
3	VDD	power_in	Power supply voltage, 2.7 to 3.6 V.
4	RST/C2CK	bidirectional	Device reset, open-drain output of internal POR or VDD monitor; an external source can reset the system by driving it low for at least 10 µs; also the clock signal for the C2 debug interface.
5	P2.0/C2D	bidirectional	Port 2.0 digital I/O (printed as 'Port 3.0' in the table) and bi-directional data signal for the C2 debug interface.
6	P1.7	bidirectional	Port 1.7 digital I/O or analog input.
7	P1.6	bidirectional	Port 1.6 digital I/O or analog input.
8	P1.5	bidirectional	Port 1.5 digital I/O or analog input.
9	P1.4	bidirectional	Port 1.4 digital I/O or analog input.
10	P1.3	bidirectional	Port 1.3 digital I/O or analog input.
11	P1.2	bidirectional	Port 1.2 digital I/O or analog input.
12	P1.1	bidirectional	Port 1.1 digital I/O or analog input.
13	P1.0	bidirectional	Port 1.0 digital I/O or analog input.
14	P0.7	bidirectional	Port 0.7 digital I/O or analog input.
15	P0.6/CNVSTR	bidirectional	Port 0.6 digital I/O or analog input, or ADC0 external convert start / IDA0 update source input.
16	P0.5	bidirectional	Port 0.5 digital I/O or analog input (UART RX0 is fixed to this pin).
17	P0.4	bidirectional	Port 0.4 digital I/O or analog input (UART TX0 is fixed to this pin).
18	P0.3/XTAL2	bidirectional	Port 0.3 digital I/O or analog input, or external clock output (crystal/resonator excitation driver, or external clock input for CMOS, capacitor or RC oscillator).
19	P0.2/XTAL1	bidirectional	Port 0.2 digital I/O or analog input, or external oscillator return for a crystal or resonator.
20	P0.1/IDA0	bidirectional	Port 0.1 digital I/O or analog input, or IDA0 current DAC analog output.
21	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	SILICON LABS
Package	QFN-20-EP(4x4)
Category	Embedded Processors & Controllers
Pins	21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Ambient temperature under bias		-55		125	°C		31
Storage Temperature		-65		150	°C		31
Voltage on any Port I/O Pin or RST with respect to GND		-0.3		5.8	V		31
Voltage on VDD with respect to GND	VDD	-0.3		4.2	V		31
Maximum Total current through VDD or GND				500	mA		31
Maximum output current sunk by RST or any Port pin				100	mA		31
Digital Supply Voltage	VRST	3		3.6	V		32
SYSCLK (System Clock)	SYSCLK	0		25	MHz		32
TSYSH (SYSCLK High Time)	TSYSH	18			ns		32
TSYSL (SYSCLK Low Time)	TSYSL	18			ns		32
Specified Operating Temperature Range		-40		85	°C		32
Digital Supply Current CPU Active	IDD		10.7	11.7	mA	VDD = 3.6 V, F = 25 MHz	32
Digital Supply Current CPU Active	IDD		7.8	8.3	mA	VDD = 3.0 V, F = 25 MHz	32
Digital Supply Current CPU Inactive (Idle)	IDD		4.8	5.2	mA	VDD = 3.6 V, F = 25 MHz	33
Digital Supply Current CPU Inactive (Idle)	IDD		3.8	4.1	mA	VDD = 3.0 V, F = 25 MHz	33
ADC0 Integral Nonlinearity	INL	-1		1	LSB		55
ADC0 Differential Nonlinearity	DNL	-1		1	LSB	Guaranteed Monotonic	55
ADC0 Offset Error		-15	0	15	LSB		55
ADC0 Full Scale Error		-15	-1	15	LSB		55
Signal-to-Noise Plus Distortion	SNDR	53	55.5		dB	10 kHz sine-wave single-ended input, 1 dB below Full Scale, 200 ksps	55
SAR Conversion Clock				3	MHz		55
Conversion Time in SAR Clocks		10			clocks		55
Track/Hold Acquisition Time		300			ns		55
Throughput Rate				200	ksps		55
Temperature Sensor Linearity		-0.2		0.2	°C		55
Temperature Sensor Absolute Accuracy		-3		3	°C		55
Temperature Sensor Gain Error		-33.5		33.5	µV/°C	Represents one standard deviation from the mean	55
Temperature Sensor Offset Error		-8.51		8.51	mV	Represents one standard deviation from the mean	55
Power Supply Current (VDD supplied to ADC0)			400	900	µA	Operating Mode, 200 ksps	55
Power Supply Rejection		-0.3		0.3	mV/V		55
IDAC Integral Nonlinearity	INL	-0.5		0.5	LSB		60
IDAC Differential Nonlinearity	DNL	-1		1	LSB	Guaranteed Monotonic	60
Gain Variation		-1		1	%	1 mA Full Scale Output Current	60
Output Voltage		2.38	2.44	2.5	V	25 °C ambient	63
VREF Short-Circuit Current				10	mA		63
Positive Hysteresis 1			0	1	mV	CP0HYP1-0 = 00	70
Positive Hysteresis 2		2	5	10	mV	CP0HYP1-0 = 01	70
Positive Hysteresis 3		7	10	20	mV	CP0HYP1-0 = 10	70
Positive Hysteresis 4		15	20	30	mV	CP0HYP1-0 = 11	70
Negative Hysteresis 1			0	1	mV	CP0HYN1-0 = 00	70
Negative Hysteresis 2		2	5	10	mV	CP0HYN1-0 = 01	70
Negative Hysteresis 3		7	10	20	mV	CP0HYN1-0 = 10	70
Negative Hysteresis 4		15	20	30	mV	CP0HYN1-0 = 11	70
Common-Mode Rejection Ratio	CMRR		1.5	4	mV/V		70
Input Offset Voltage		-5		5	mV		70
RST Output Low Voltage				0.6	V	IOL = 8.5 mA, VDD = 2.7 V to 3.6 V	102
VDD POR Threshold (VRST)	VRST	2.4	2.55	2.7	V		102
Missing Clock Detector Timeout		100	220	600	µs	Time from last system clock rising edge to reset initiation	102
Reset Time Delay				32	µs	Delay between release of any reset source and code execution at location 0x0000	102
Minimum RST Low Time to Generate a System Reset		15			µs		102
VDD Monitor Turn-on Time		100			µs		102
VDD Monitor Supply Current			20	50	µA		102
Erase Cycle Time		10	15	20	ms	25 MHz System Clock	104
Write Cycle Time		40	55	70	µs	25 MHz System Clock	104
Endurance		20	100		k Erase/Write		104
Internal High-Frequency Oscillator Frequency		24	24.5	25	MHz	IFCN = 11b	122
Internal Low-Frequency Oscillator Frequency		72	80	88	kHz	OSCLD = 11b	122
ADC0 Input Capacitance			5		pF		55
Digital Supply RAM Data Retention Voltage			1.5		V		32

CAD (KiCad official)

Symbol: C8051F330-GM
Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
3D model: QFN-20-EP(4x4) (KiCad packages3D, STEP)
3D model files: c8051f330-gm-etched.step / c8051f330-gm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); c8051f330-gm.step / c8051f330-gm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: SILICON LABS datasheet (214 pp, sha256 f08c94bae517d610, retrieved 2026-11-10, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

C8051F330-GM

Verified C8051F330-GM

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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