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PIC16F887-I

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Microchip Tech Microcontrollers (MCU/MPU/SOC), TQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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PIC16F887-I

Microchip Tech · Microcontrollers (MCU/MPU/SOC) · TQFP-44(10x10)

PIC16F887-I from Microchip Tech, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RC7/RX/DT bidirectional PORTC bit 7 general purpose I/O, EUSART asynchronous receive input (RX) or synchronous data (DT).
2 RD4 bidirectional PORTD bit 4 general purpose I/O.
3 RD5/P1B bidirectional PORTD bit 5 general purpose I/O or P1B PWM output.
4 RD6/P1C bidirectional PORTD bit 6 general purpose I/O or P1C PWM output.
5 RD7/P1D bidirectional PORTD bit 7 general purpose I/O or P1D PWM output.
6 VSS power_in Ground reference.
7 VDD power_in Positive supply.
8 RB0/AN12/INT bidirectional PORTB bit 0 general purpose I/O with interrupt-on-change and weak pull-up, A/D channel 12 input, or external interrupt (INT).
9 RB1/AN10/C12IN3- bidirectional PORTB bit 1 general purpose I/O with interrupt-on-change and weak pull-up, A/D channel 10 input, or comparator C1/C2 negative input.
10 RB2/AN8 bidirectional PORTB bit 2 general purpose I/O with interrupt-on-change and weak pull-up, or A/D channel 8 input.
11 RB3/AN9/PGM/C12IN2- bidirectional PORTB bit 3 general purpose I/O with interrupt-on-change and weak pull-up, A/D channel 9 input, low-voltage ICSP programming enable (PGM), or comparator C1/C2 negative input.
12 NC unconnected No connection.
13 NC unconnected No connection.
14 RB4/AN11 bidirectional PORTB bit 4 general purpose I/O with interrupt-on-change and weak pull-up, or A/D channel 11 input.
15 RB5/AN13/T1G bidirectional PORTB bit 5 general purpose I/O with interrupt-on-change and weak pull-up, A/D channel 13 input, or Timer1 gate input.
16 RB6/ICSPCLK bidirectional PORTB bit 6 general purpose I/O with interrupt-on-change and weak pull-up, or ICSP serial programming clock.
17 RB7/ICSPDAT bidirectional PORTB bit 7 general purpose I/O with interrupt-on-change and weak pull-up, or ICSP data I/O.
18 RE3/MCLR/VPP input General purpose input, Master Clear (MCLR) with internal pull-up, or high-voltage programming input (VPP).
19 RA0/AN0/ULPWU/C12IN0- bidirectional PORTA bit 0 general purpose I/O, A/D channel 0 input, Ultra Low-Power Wake-up input, or comparator C1/C2 negative input.
20 RA1/AN1/C12IN1- bidirectional PORTA bit 1 general purpose I/O, A/D channel 1 input, or comparator C1/C2 negative input.
21 RA2/AN2/VREF-/CVREF/C2IN+ bidirectional PORTA bit 2 general purpose I/O, A/D channel 2, A/D negative voltage reference input, comparator voltage reference output, or comparator C2 positive input.
22 RA3/AN3/VREF+/C1IN+ bidirectional PORTA bit 3 general purpose I/O, A/D channel 3, A/D positive voltage reference input, or comparator C1 positive input.
23 RA4/T0CKI/C1OUT bidirectional PORTA bit 4 general purpose I/O, Timer0 clock input, or comparator C1 output.
24 RA5/AN4/SS/C2OUT bidirectional PORTA bit 5 general purpose I/O, A/D channel 4, SPI Slave Select input, or comparator C2 output.
25 RE0/AN5 bidirectional PORTE bit 0 general purpose I/O or A/D channel 5 input.
26 RE1/AN6 bidirectional PORTE bit 1 general purpose I/O or A/D channel 6 input.
27 RE2/AN7 bidirectional PORTE bit 2 general purpose I/O or A/D channel 7 input.
28 VDD power_in Positive supply.
29 VSS power_in Ground reference.
30 RA7/OSC1/CLKIN bidirectional PORTA bit 7 general purpose I/O, crystal/resonator connection (OSC1), or external clock input/RC oscillator connection (CLKIN).
31 RA6/OSC2/CLKOUT bidirectional PORTA bit 6 general purpose I/O, crystal/resonator connection (OSC2), or FOSC/4 output (CLKOUT).
32 RC0/T1OSO/T1CKI bidirectional PORTC bit 0 general purpose I/O, Timer1 oscillator output, or Timer1 clock input.
33 NC unconnected No connection.
34 NC unconnected No connection.
35 RC1/T1OSI/CCP2 bidirectional PORTC bit 1 general purpose I/O, Timer1 oscillator input, or Capture/Compare/PWM2.
36 RC2/P1A/CCP1 bidirectional PORTC bit 2 general purpose I/O, P1A PWM output, or Capture/Compare/PWM1.
37 RC3/SCK/SCL bidirectional PORTC bit 3 general purpose I/O, SPI clock (SCK), or I2C clock (SCL, open drain).
38 RD0 bidirectional PORTD bit 0 general purpose I/O.
39 RD1 bidirectional PORTD bit 1 general purpose I/O.
40 RD2 bidirectional PORTD bit 2 general purpose I/O.
41 RD3 bidirectional PORTD bit 3 general purpose I/O.
42 RC4/SDI/SDA bidirectional PORTC bit 4 general purpose I/O, SPI data input (SDI), or I2C data input/output (SDA, open drain).
43 RC5/SDO bidirectional PORTC bit 5 general purpose I/O or SPI data output (SDO).
44 RC6/TX/CK bidirectional PORTC bit 6 general purpose I/O, EUSART asynchronous transmit (TX), or synchronous clock (CK).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-44(10x10)
Category Embedded Processors & Controllers
Pins 44

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Voltage on VDD with respect to VSS -0.3 6.5 V 249
Voltage on MCLR with respect to VSS -0.3 13.5 V 249
Voltage on all other pins with respect to VSS -0.3 V 249
Ambient temperature under bias -40 125 °C 249
Storage temperature -65 150 °C 249
Maximum current out of VSS pin 95 mA 249
Maximum current into VDD pin 95 mA 249
Maximum output current sunk by any I/O pin 25 mA 249
Maximum output current sourced by any I/O pin 25 mA 249
Operating temperature (Industrial, -I) TA -40 85 °C Industrial (-I) grade 251
VDD Supply Voltage VDD 2 5.5 V FOSC <= 8 MHz: HFINTOSC, EC 251
VDD Supply Voltage VDD 3 5.5 V FOSC <= 10 MHz 251
VDD Supply Voltage VDD 4.5 5.5 V FOSC <= 20 MHz 251
RAM Data Retention Voltage VDR 1.5 V Device in Sleep mode 251
VDD Rise Rate to ensure internal Power-on Reset signal SVDD 0.05 V/ms See Section 14.2.1 Power-on Reset (POR) for details 251
I/O port VIL with TTL buffer VIL 0.8 V 4.5V <= VDD <= 5.5V 255
OSC1 input low voltage (XT and LP modes) VIL 0.3 V XT and LP modes 255
I/O port VIH with TTL buffer VIH 2 V 4.5V <= VDD <= 5.5V 255
OSC1 input high voltage (XT and LP modes) VIH 1.6 V XT and LP modes 255
I/O ports input leakage current IIL 0.1 1 µA VSS <= VPIN <= VDD, pin at high-impedance 255
MCLR input leakage current IIL 0.1 5 µA VSS <= VPIN <= VDD 255
OSC1 input leakage current IIL 0.1 5 µA VSS <= VPIN <= VDD, XT, HS and LP oscillator configuration 255
PORTB weak pull-up current IPUR 50 250 400 µA VDD = 5.0V, VPIN = VSS 255
I/O ports output low voltage VOL 0.6 V IOL = 8.5 mA, VDD = 4.5V (Ind.) 255
OSC2 pin capacitance COSC2 15 pF In XT, HS and LP modes when external clock is used to drive OSC1 256
All I/O pins capacitance CIO 50 pF 256
VDD for Read/Write (EECON1) VDRW 5.5 V Using EECON1 to read/write 256
Data EEPROM Erase/Write Cycle Time TDEW 5 6 ms 256
Data EEPROM Characteristic Retention TRETD 40 Year Provided no other specifications are violated 256
VDD for Read (program Flash) VPR 5.5 V VMIN = Minimum operating voltage 256
VDD for Row Erase/Write (program Flash) VPEW 5.5 V 256
VDD for Bulk Erase Operations 4.5 5.5 V 256
Program Flash Erase/Write cycle time TPEW 2 2.5 ms 256
Program Flash Characteristic Retention TRETD 40 Year Provided no other specifications are violated 256
Supply current IDD, LP oscillator IDD 13 19 µA VDD 2.0V; FOSC = 32 kHz; LP Oscillator mode 252
Supply current IDD, LP oscillator IDD 22 30 µA VDD 3.0V; FOSC = 32 kHz; LP Oscillator mode 252
Supply current IDD, LP oscillator IDD 33 60 µA VDD 5.0V; FOSC = 32 kHz; LP Oscillator mode 252
Supply current IDD, XT oscillator IDD 280 380 µA VDD 2.0V; FOSC = 4 MHz; XT Oscillator mode 252
Supply current IDD, XT oscillator IDD 480 670 µA VDD 3.0V; FOSC = 4 MHz; XT Oscillator mode 252
Supply current IDD, XT oscillator IDD 0.9 1.4 mA VDD 5.0V; FOSC = 4 MHz; XT Oscillator mode 252
Supply current IDD, HFINTOSC IDD 0.65 0.9 mA VDD 2.0V; FOSC = 8 MHz; HFINTOSC mode 252
Supply current IDD, HFINTOSC IDD 1.01 1.3 mA VDD 3.0V; FOSC = 8 MHz; HFINTOSC mode 252
Supply current IDD, HFINTOSC IDD 1.86 2.3 mA VDD 5.0V; FOSC = 8 MHz; HFINTOSC mode 252
Power-down base current IPD IPD 0.05 1.2 µA VDD 2.0V; WDT, BOR, Comparators, VREF and T1OSC disabled 253
Power-down base current IPD IPD 0.15 1.5 µA VDD 3.0V; WDT, BOR, Comparators, VREF and T1OSC disabled 253
Power-down base current IPD IPD 0.35 1.8 µA VDD 5.0V; WDT, BOR, Comparators, VREF and T1OSC disabled 253
Internal calibrated HFINTOSC frequency HFOSC 7.92 8 8.08 MHz Tolerance 1%; VDD = 3.5V, 25°C 260
Internal calibrated HFINTOSC frequency HFOSC 7.84 8 8.16 MHz Tolerance 2%; 2.5V <= VDD <= 5.5V, 0°C <= TA <= +85°C 260
Internal calibrated HFINTOSC frequency HFOSC 7.6 8 8.4 MHz Tolerance 5%; 2.0V <= VDD <= 5.5V, -40°C <= TA <= +85°C (Ind.) 260
Internal uncalibrated LFINTOSC frequency LFOSC 15 31 45 kHz 260
Power-up Timer period TPWRT 40 65 140 ms 263
Watchdog Timer time-out period (no prescaler) TWDT 10 16 29 ms VDD = 5V, -40°C to +85°C 263
Brown-out Reset voltage (BOR4V = 0) VBOR 2 2.2 V BOR4V bit = 0 263
Brown-out Reset voltage (BOR4V = 1) VBOR 3.6 4 4.4 V BOR4V bit = 1, -40°C to +85°C 263
Thermal resistance junction to ambient, 44-pin TQFP JA 45.8 °C/W 44-pin TQFP package 257
Thermal resistance junction to case, 44-pin TQFP JC 14.5 °C/W 44-pin TQFP package 257
Junction temperature TJ 150 °C For derated power calculations 257

CAD (KiCad official)

  • Symbol: PIC16F887-I
  • Footprint: Package_QFP:TQFP-44_10x10mm_P0.8mm
  • 3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
  • 3D model files: pic16f887-i-etched.step / pic16f887-i-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); pic16f887-i.step / pic16f887-i.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (338 pp, sha256 54a84d1486aaf5af, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF