component
MIC2185YQS
Public Made by Adomby adom
Microchip Tech DC-DC Controllers, QSOP-16-150mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMIC2185YQS
Microchip Tech · DC-DC Controllers · QSOP-16-150mil
MIC2185YQS from Microchip Tech, in a QSOP-16-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VINA | power_in | Input voltage to control circuitry, 2.9V to 14V. |
| 2 | SKIP | input | Regulator operates in PWM mode when pulled low and in skip mode when raised to VDD; no automatic switching between modes. |
| 3 | SS | passive | Soft-start capacitor pin; a 5µA current source charges the capacitor up to VDD to slow the output voltage rise and reduce inrush current. |
| 4 | COMP | output | Internal error amplifier output; connect a capacitor or series RC network to compensate the control loop. |
| 5 | SGND | power_in | Small signal ground return, routed separately from other grounds to the (-) terminal of COUT. |
| 6 | FB | input | Feedback input that regulates FB to 1.245V. |
| 7 | EN/UVLO | input | Enable/undervoltage lockout input; below 1.5V (typ) switching is disabled, below 0.9V (typ) the device enters micropower shutdown with under 0.5µA quiescent current, and the 1.5V UVLO threshold has 140mV hysteresis. |
| 8 | VREF | power_out | 1.245V reference output; connect a 0.1µF capacitor to SGND. |
| 9 | CSH | input | Current sense (+) input to the current limit comparator and current amplifier; a built-in 100mV (typ) offset sets the current limit threshold with the sense resistor. |
| 10 | VDD | power_out | 3V internal linear-regulator output and chip supply bus; bypass to SGND with 1µF, maximum source current 0.5mA. |
| 11 | SYNC | input | Frequency synchronization input; the leading edge of an external clock above 1.4V (typ) starts a switching cycle, connect to SGND if not used. |
| 12 | PGND | power_in | MOSFET driver power ground return, connecting the bottom of the current sense resistor and the (-) terminal of CIN. |
| 13 | OUTN | output | N-channel MOSFET gate drive output swinging from ground to VINP, with typical on-resistance of 5Ω. |
| 14 | OUTP | output | Synchronous P-channel MOSFET gate drive output swinging from ground to VINP, with typical on-resistance of 5Ω. |
| 15 | FREQ/2 | input | Frequency divider input; low gives 400kHz oscillator frequency, raised to VDD gives 200kHz. |
| 16 | VINP | power_in | Power input to the gate drive circuitry, 2.9V to 14V, typically connected to the output voltage to enhance gate drive. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | QSOP-16-150mil |
| Category | Power Management ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Feedback Voltage Reference (±1%) | VFB | 1.233 | 1.245 | 1.258 | V | TJ=25°C | 3 |
| Feedback Voltage Reference (±2%) | VFB | 1.22 | 1.27 | V | -40°C<TJ<+125°C | 3 | |
| Feedback Voltage Reference (±3%) | VFB | 1.208 | 1.245 | 1.282 | V | 3V ≤ VINA ≤ 9V; 0mV ≤ CSH ≤ 75mV | 3 |
| Digital Supply Voltage | VDD | 2.8 | 3 | 3.2 | V | IL = 0 | 3 |
| Undervoltage Lockout VDD upper threshold (turn on) | 2.75 | 2.9 | V | VDD upper threshold (turn on threshold) | 3 | ||
| Reference Voltage (±1.5%) | VREF | 1.226 | 1.245 | 1.264 | V | TJ=25°C | 3 |
| Reference Voltage (±2.5%) | VREF | 1.213 | 1.276 | V | -40°C<TJ<+125°C | 3 | |
| Enable Input Threshold | 0.6 | 0.9 | 1.2 | V | 3 | ||
| UVLO Threshold | 1.4 | 1.5 | 1.6 | V | 3 | ||
| Enable Input Current | 0.2 | 5 | µA | VEN/UVLO = 5V | 3 | ||
| SKIP Threshold | 0.6 | 1.4 | 2.2 | V | 4 | ||
| SKIP Input Current | 0.1 | 5 | µA | VSKIP = 3V | 4 | ||
| Oscillator Frequency | fS | 360 | 400 | 440 | kHz | 4 | |
| FREQ/2 frequency | fS | 170 | 200 | 230 | kHz | VFREQ/2=3V | 4 |
| SYNC Threshold Level | 0.6 | 1.4 | 2.2 | V | 4 | ||
| SYNC Input Current | 0.1 | 5 | µA | 4 | |||
| SYNC Capture Range | 600 | kHz | Note 4 | 4 | |||
| Output Driver Impedance Source | 4 | 8 | Ω | Source; VINP = 12V | 4 | ||
| Output Driver Impedance Sink | 3 | 7 | Ω | Sink; VINP = 12V | 4 | ||
| Output Driver Impedance Source | 5 | 11 | Ω | Source; VINP = 5V | 4 | ||
| Output Driver Impedance Sink | 5 | 11 | Ω | Sink; VINP = 5V | 4 | ||
| Supply Voltage (VINA, VINP) | 2.9 | 14 | V | Operating Ratings | 3 | ||
| Operating Ambient Temperature | TA | -40 | 85 | °C | 3 | ||
| Junction Temperature | TJ | -40 | 125 | °C | 3 | ||
| Supply Voltage (VINA, VINP) | 15 | V | 3 | ||||
| Digital Supply Voltage (VDD) | VDD | 7 | V | 3 | |||
| Skip Pin Voltage | VSKIP | -0.3 | 7 | V | 3 | ||
| Comp Pin Voltage | VCOMP | -0.3 | 3 | V | 3 | ||
| Feedback Pin Voltage | VFB | -0.3 | 3 | V | 3 | ||
| Enable Pin Voltage | VEN/UVLO | -0.3 | 15 | V | 3 | ||
| Current Sense Voltage | VCSH | -0.3 | 1 | V | 3 | ||
| Sync Pin Voltage | VSYNC | -0.3 | 7 | V | 3 | ||
| Freq/2 Pin Voltage | VFREQ/2 | -0.3 | 7 | V | 3 | ||
| Ambient Storage Temp | -65 | 150 | °C | 3 | |||
| Feedback Bias Current | 50 | nA | 3 | ||||
| Output Voltage Line Regulation | 0.08 | %/V | 3V ≤ VINA ≤ 9V | 3 | |||
| Output Voltage Load Regulation | -1.2 | % | 0mV ≤ CSH ≤ 75mV | 3 | |||
| VINA Input Current, PWM mode | 0.8 | mA | VSKIP = 0V | 3 | |||
| VINP Input Current, PWM mode | 3.8 | mA | VSKIP = 0V (excluding external MOSFET gate current) | 3 | |||
| VINA Input Current, SKIP mode | 0.6 | mA | VSKIP = 5V | 3 | |||
| Shutdown Quiescent Current | 0.5 | µA | VEN/UVLO = 0V; (IVINA + IVINP) | 3 | |||
| Current Limit Threshold Voltage | 100 | mV | Voltage on CSH to trip current limit | 4 | |||
| Maximum Duty Cycle | 85 | % | VFB = 1.0V | 4 |
CAD (KiCad official)
- Symbol:
MIC2185YQS - Footprint:
Package_SO:QSOP-16_3.9x4.9mm_P0.635mm - 3D model: QSOP-16-150mil (KiCad packages3D, STEP)
- 3D model files:
mic2185yqs-etched.step/mic2185yqs-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mic2185yqs.step/mic2185yqs.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (15 pp, sha256
559d33d56583c4c1, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).