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AD7266BSUZ-REEL
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADC), TQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README
markdownAD7266BSUZ-REEL
Analog Devices · Analog To Digital Converters (ADC) · TQFP-32(7x7)
AD7266BSUZ-REEL from Analog Devices, in a TQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DGND | power_in | Digital ground reference for all digital circuitry; both DGND pins connect to the system DGND plane and must not be more than 0.3 V from AGND, even on a transient basis. |
| 2 | REF SELECT | input | Logic input for reference selection: tied to DGND uses the on-chip 2.5 V reference for both ADCs, while a logic high allows an external reference through DCAPA and/or DCAPB. |
| 3 | AVDD | power_in | Analog supply voltage of 2.7 V to 5.25 V, the only supply for all analog circuitry, which must stay within 0.3 V of DVDD and be decoupled to AGND. |
| 4 | DCAPA | passive | Decoupling capacitor pin for the ADC A reference buffer, where 470 nF is recommended and a buffered on-chip reference can be taken or an external reference applied, depending on the selected input range. |
| 5 | AGND | power_in | Analog ground reference for all analog circuitry; all three AGND pins connect to the system AGND plane and must not be more than 0.3 V from DGND. |
| 6 | AGND | power_in | Analog ground reference for all analog circuitry; all three AGND pins connect to the system AGND plane and must not be more than 0.3 V from DGND. |
| 7 | VA1 | passive | Analog input of ADC A, programmable as one of six single-ended channels or as one of three true differential pairs. |
| 8 | VA2 | passive | Analog input of ADC A, programmable as one of six single-ended channels or as one of three true differential pairs. |
| 9 | VA3 | passive | Analog input of ADC A, programmable as one of six single-ended channels or as one of three true differential pairs. |
| 10 | VA4 | passive | Analog input of ADC A, programmable as one of six single-ended channels or as one of three true differential pairs. |
| 11 | VA5 | passive | Analog input of ADC A, programmable as one of six single-ended channels or as one of three true differential pairs. |
| 12 | VA6 | passive | Analog input of ADC A, programmable as one of six single-ended channels or as one of three true differential pairs. |
| 13 | VB6 | passive | Analog input of ADC B, programmable as one of six single-ended channels or as one of three true differential pairs. |
| 14 | VB5 | passive | Analog input of ADC B, programmable as one of six single-ended channels or as one of three true differential pairs. |
| 15 | VB4 | passive | Analog input of ADC B, programmable as one of six single-ended channels or as one of three true differential pairs. |
| 16 | VB3 | passive | Analog input of ADC B, programmable as one of six single-ended channels or as one of three true differential pairs. |
| 17 | VB2 | passive | Analog input of ADC B, programmable as one of six single-ended channels or as one of three true differential pairs. |
| 18 | VB1 | passive | Analog input of ADC B, programmable as one of six single-ended channels or as one of three true differential pairs. |
| 19 | AGND | power_in | Analog ground reference for all analog circuitry; all three AGND pins connect to the system AGND plane and must not be more than 0.3 V from DGND. |
| 20 | DCAPB | passive | Decoupling capacitor pin for the ADC B reference buffer, where 470 nF is recommended and a buffered on-chip reference can be taken or an external reference applied, depending on the selected input range. |
| 21 | RANGE | input | Logic input setting the analog input range: tied low selects 0 V to VREF, and a logic high when CS goes low selects 2 × VREF. |
| 22 | SGL/DIFF | input | Logic input selecting differential pairs when low and single-ended operation when high. |
| 23 | A2 | input | Multiplexer select logic input choosing the channel pair converted simultaneously, which must be set before the acquisition time and the falling edge of CS. |
| 24 | A1 | input | Multiplexer select logic input choosing the channel pair converted simultaneously, which must be set before the acquisition time and the falling edge of CS. |
| 25 | A0 | input | Multiplexer select logic input choosing the channel pair converted simultaneously, which must be set before the acquisition time and the falling edge of CS. |
| 26 | CS | input | Active-low chip select that initiates conversions on its falling edge and frames the serial data transfer. |
| 27 | SCLK | input | Serial clock logic input that clocks data out of the AD7266 and also serves as the conversion clock source. |
| 28 | DOUTB | output | Serial data output for ADC B, clocked out on the SCLK falling edge with 14 SCLKs needed to read the MSB-first data (two leading zeros then 12 data bits). |
| 29 | DGND | power_in | Digital ground reference for all digital circuitry; both DGND pins connect to the system DGND plane and must not be more than 0.3 V from AGND, even on a transient basis. |
| 30 | DOUTA | output | Serial data output for ADC A, clocked out on the SCLK falling edge with 14 SCLKs needed to read the MSB-first data (two leading zeros then 12 data bits). |
| 31 | VDRIVE | power_in | Logic power supply input that sets the interface voltage, must be decoupled to DGND, and should never exceed AVDD or DVDD by more than 0.3 V. |
| 32 | DVDD | power_in | Digital supply voltage of 2.7 V to 5.25 V, the supply for all digital circuitry, which must stay within 0.3 V of AVDD and be decoupled to DGND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TQFP-32(7x7) |
| Category | Data Acquisition |
| Pins | 32 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Signal-to-Noise Ratio (SNR), differential mode | 71 | dB | fIN = 50 kHz sine wave; differential mode | 3 | |||
| Signal-to-Noise Ratio (SNR), single-ended and pseudo differential modes | 69 | dB | fIN = 50 kHz sine wave; single-ended and pseudo differential modes | 3 | |||
| Signal-to-Noise + Distortion (SINAD), differential mode | 70 | dB | fIN = 50 kHz sine wave; differential mode | 3 | |||
| Signal-to-Noise + Distortion (SINAD), single-ended and pseudo differential modes | 68 | dB | fIN = 50 kHz sine wave; single-ended and pseudo differential modes | 3 | |||
| Total Harmonic Distortion (THD), differential mode | -77 | dB | fIN = 50 kHz sine wave; differential mode | 3 | |||
| Total Harmonic Distortion (THD), single-ended and pseudo differential modes | -73 | dB | fIN = 50 kHz sine wave; single-ended and pseudo differential modes | 3 | |||
| Spurious-Free Dynamic Range (SFDR) | -75 | dB | fIN = 50 kHz sine wave | 3 | |||
| Aperture Delay | 11 | ns | 3 | ||||
| Aperture Delay Matching | 200 | ps | 3 | ||||
| Integral Nonlinearity (INL), differential mode | -1 | 1 | LSB | differential mode | 3 | ||
| Integral Nonlinearity (INL), single-ended and pseudo differential modes | -1.5 | 1.5 | LSB | single-ended and pseudo differential modes | 3 | ||
| Differential Nonlinearity (DNL), differential mode | -0.99 | 0.99 | LSB | Differential mode | 3 | ||
| Differential Nonlinearity (DNL), single-ended and pseudo differential modes | -0.99 | 1.5 | LSB | Single-ended and pseudo differential modes | 3 | ||
| Offset Error (straight binary output coding) | -7 | 7 | LSB | 3 | |||
| Gain Error (straight binary output coding) | -2.5 | 2.5 | LSB | 3 | |||
| Positive Gain Error (twos complement output coding) | -2 | 2 | LSB | 3 | |||
| Zero Code Error (twos complement output coding) | -5 | 5 | LSB | 3 | |||
| Negative Gain Error (twos complement output coding) | -2 | 2 | LSB | 3 | |||
| DC Leakage Current (analog input) | -1 | 1 | μA | 4 | |||
| Reference Output Voltage | 2.5 | 2.5 | V | Relates to pin DCAPA or pin DCAPB | 4 | ||
| Reference Output Voltage tolerance | -0.2 | 0.2 | % | @ 25°C | 4 | ||
| Reference Input Voltage Range | 0.1 | V | See Typical Performance Characteristics section | 4 | |||
| DC Leakage Current (reference input) | -2 | 2 | μA | External reference applied to Pin DCAPA/Pin DCAPB | 4 | ||
| Reference Temperature Coefficient | 20 | ppm/°C | 4 | ||||
| Input High Voltage | VINH | 2.8 | V | 4 | |||
| Input Low Voltage | VINL | 0.4 | V | 4 | |||
| Output Low Voltage | VOL | 0.4 | V | 4 | |||
| Floating State Leakage Current | -1 | 1 | μA | 4 | |||
| Track-and-Hold Acquisition Time | 90 | ns | Full-scale step input; VDD = 5 V | 4 | |||
| Track-and-Hold Acquisition Time | 110 | ns | Full-scale step input; VDD = 3 V | 4 | |||
| Throughput Rate | 2 | MSPS | 4 | ||||
| VDD supply voltage | VDD | 2.7 | 5.25 | V | 4 | ||
| VDRIVE supply voltage | VDRIVE | 2.7 | 5.25 | V | 4 | ||
| IDD Normal Mode (Static) | IDD | 2.3 | mA | VDD = 5.25 V | 4 | ||
| IDD Operational, fS = 2 MSPS | IDD | 5.7 | 6.4 | mA | VDD = 5.25 V | 4 | |
| IDD Operational, fS = 1.5 MSPS | IDD | 3.4 | 4 | mA | VDD = 3.6 V | 4 | |
| IDD Partial Power-Down Mode | IDD | 500 | μA | Static | 4 | ||
| IDD Full Power-Down Mode (VDD) | IDD | 1 | μA | TA = −40°C to +85°C | 4 | ||
| IDD Full Power-Down Mode (VDD) | IDD | 2.8 | μA | TA > 85°C to 125°C | 4 | ||
| Power Dissipation, Normal Mode (Operational) | 33.6 | mW | VDD = 5.25 V | 4 | |||
| Power Dissipation, Partial Power-Down (Static) | 2.625 | mW | VDD = 5.25 V | 4 | |||
| Power Dissipation, Full Power-Down (Static) | 5.25 | μW | VDD = 5.25 V, TA = −40°C to +85°C | 4 | |||
| SCLK frequency (fSCLK) | fSCLK | 1 | MHz | TA = −40°C to +85°C | 5 | ||
| SCLK frequency (fSCLK) | fSCLK | 4 | MHz | TA > 85°C to 125°C | 5 | ||
| SCLK frequency (fSCLK) | fSCLK | 32 | MHz | 5 | |||
| Conversion time (tCONVERT) | tCONVERT | 437.5 | ns | fSCLK = 32 MHz, VDD = 5 V, fSAMPLE = 2 MSPS | 5 | ||
| Quiet time (tQUIET) | tQUIET | 30 | ns | Minimum time between end of serial read and next falling edge of CS | 5 | ||
| Data access time after SCLK falling edge (t4) | t4 | 36 | ns | VDD = 3 V | 5 | ||
| Data access time after SCLK falling edge (t4) | t4 | 27 | ns | VDD = 5 V | 5 | ||
| VDD to AGND | VDD | -0.3 | 7 | V | 6 | ||
| DVDD to DGND | DVDD | -0.3 | 7 | V | 6 | ||
| AVDD to DVDD | -0.3 | 0.3 | V | 6 | |||
| AGND to DGND | -0.3 | 0.3 | V | 6 | |||
| Digital Input Voltage to DGND | -0.3 | 7 | V | 6 | |||
| Input Current to Any Pin Except Supplies | -10 | 10 | mA | Except supplies | 6 | ||
| Operating Temperature Range | -40 | 125 | °C | 6 | |||
| Storage Temperature Range | -65 | 150 | °C | 6 | |||
| Junction Temperature | 150 | °C | 6 | ||||
| Lead Temperature, Reflow | 255 | °C | Reflow temperature (10 to 30 sec) | 6 | |||
| Thermal Impedance, junction-to-ambient (θJA), TQFP | θJA | 55 | °C/W | TQFP package | 6 |
CAD (KiCad official)
- Symbol:
AD7266BSUZ-REEL - Footprint:
Package_QFP:TQFP-32_7x7mm_P0.8mm - 3D model: TQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files:
ad7266bsuz-reel-etched.step/ad7266bsuz-reel-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7266bsuz-reel.step/ad7266bsuz-reel.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (28 pp, sha256
ef619f55aa5e6d94, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).