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SN74HCS137DR

Public Made by Adom

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Texas Instruments Signal Switches, Multiplexers, Decoders, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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SN74HCS137DR

Texas Instruments · Signal Switches, Multiplexers, Decoders · SOIC-16

SN74HCS137DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Address select 0 input for the 3-to-8 decoder, which is held in the address latch when LE is high.
2 A1 input Address select 1 input for the 3-to-8 decoder, which is held in the address latch when LE is high.
3 A2 input Address select 2 input for the 3-to-8 decoder, which is held in the address latch when LE is high.
4 LE input Active-low latch enable; when low the device acts as a standard decoder, and when high the address latch retains its previous state.
5 G1 input Active-low strobe input 1; when it or G0 gates the outputs, all outputs are forced high.
6 G0 input Strobe input 0 (active-high standard output strobe); when it or G1 gates the outputs, all outputs are forced high.
7 Y7 output Decoder output 7, low only when it is the selected output and the outputs are not strobed off.
8 GND power_in Ground reference pin.
9 Y6 output Decoder output 6, low only when it is the selected output and the outputs are not strobed off.
10 Y5 output Decoder output 5, low only when it is the selected output and the outputs are not strobed off.
11 Y4 output Decoder output 4, low only when it is the selected output and the outputs are not strobed off.
12 Y3 output Decoder output 3, low only when it is the selected output and the outputs are not strobed off.
13 Y2 output Decoder output 2, low only when it is the selected output and the outputs are not strobed off.
14 Y1 output Decoder output 1, low only when it is the selected output and the outputs are not strobed off.
15 Y0 output Decoder output 0, low only when it is the selected output and the outputs are not strobed off.
16 VCC power_in Positive supply pin; recommended supply range is 2 V to 6 V with absolute maximum of 7 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC Supply voltage VCC 2 5 6 V 4
Ambient temperature TA -40 125 °C 4
Supply voltage VCC -0.5 7 V 4
Input clamp current IIK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Output clamp current IOK -20 20 mA VI < -0.5 V or VI > VCC + 0.5 V 4
Continuous output current IO -35 35 mA VO = 0 to VCC 4
Continuous current through VCC or GND -70 70 mA 4
Junction temperature TJ 150 °C 4
Storage temperature Tstg -65 150 °C 4
Junction-to-ambient thermal resistance (D, SOIC-16) RθJA 122.2 °C/W 4
Positive switching threshold VT+ 0.7 1.5 V VCC = 2 V 5
Positive switching threshold VT+ 1.7 3.15 V VCC = 4.5 V 5
Positive switching threshold VT+ 2.1 4.2 V VCC = 6 V 5
Negative switching threshold VT- 0.3 1 V VCC = 2 V 5
Negative switching threshold VT- 0.9 2.2 V VCC = 4.5 V 5
Negative switching threshold VT- 1.2 3 V VCC = 6 V 5
Hysteresis (VT+ - VT-) ΔVT 0.2 1 V VCC = 2 V 5
Hysteresis (VT+ - VT-) ΔVT 0.4 1.4 V VCC = 4.5 V 5
Hysteresis (VT+ - VT-) ΔVT 0.6 1.6 V VCC = 6 V 5
High-level output voltage VOH 4 4.3 V VI = VIH or VIL; IOH = -6 mA; VCC = 4.5 V 5
High-level output voltage VOH 5.4 5.75 V VI = VIH or VIL; IOH = -7.8 mA; VCC = 6 V 5
Low-level output voltage VOL 0.002 0.1 V VI = VIH or VIL; IOL = 20 µA; VCC 2 V to 6 V 5
Low-level output voltage VOL 0.18 0.3 V VI = VIH or VIL; IOL = 6 mA; VCC = 4.5 V 5
Low-level output voltage VOL 0.22 0.33 V VI = VIH or VIL; IOL = 7.8 mA; VCC = 6 V 5
Input leakage current II -1000 100 1000 nA VI = VCC or 0; VCC = 6 V 5
Supply current ICC 0.1 2 µA VI = VCC or 0, IO = 0; VCC = 6 V 5
Propagation delay An to Y tpd 17 35 ns CL = 50 pF; TA = 25°C; VCC = 2 V 6
Propagation delay An to Y tpd 51 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V 6
Propagation delay An to Y tpd 7 14 ns CL = 50 pF; TA = 25°C; VCC = 4.5 V 6
Propagation delay An to Y tpd 20 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V 6
Propagation delay An to Y tpd 6 12 ns CL = 50 pF; TA = 25°C; VCC = 6 V 6
Propagation delay An to Y tpd 17 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V 6
Propagation delay G or G1 to Y tpd 15 30 ns CL = 50 pF; TA = 25°C; VCC = 2 V 6
Propagation delay G or G1 to Y tpd 48 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V 6
Propagation delay G or G1 to Y tpd 7 11 ns CL = 50 pF; TA = 25°C; VCC = 4.5 V 6
Propagation delay G or G1 to Y tpd 17 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V 6
Propagation delay G or G1 to Y tpd 6 9 ns CL = 50 pF; TA = 25°C; VCC = 6 V 6
Propagation delay G or G1 to Y tpd 15 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V 6
Propagation delay LE to Y tpd 18 39 ns CL = 50 pF; TA = 25°C; VCC = 2 V 6
Propagation delay LE to Y tpd 60 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V 6
Propagation delay LE to Y tpd 8 16 ns CL = 50 pF; TA = 25°C; VCC = 4.5 V 6
Propagation delay LE to Y tpd 24 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V 6
Propagation delay LE to Y tpd 7 15 ns CL = 50 pF; TA = 25°C; VCC = 6 V 6
Propagation delay LE to Y tpd 21 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 6 V 6
Pulse duration LE pulse width tw 9 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V 5
Pulse duration LE pulse width tw 7 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 4.5 V 5
Setup time An to LE tsu 4 ns CL = 50 pF; TA = 25°C; VCC = 2 V 5
Setup time An to LE tsu 5 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V 5
Setup time An to LE tsu 3 ns CL = 50 pF; TA = 25°C; VCC = 4.5 V 5
Hold time An to LE th 4 ns CL = 50 pF; TA = 25°C; VCC = 2 V 5
Hold time An to LE th 5 ns CL = 50 pF; TA = -40°C to 125°C; VCC = 2 V 5

CAD (KiCad official)

  • Symbol: SN74HCS137DR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: sn74hcs137dr-etched.step / sn74hcs137dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn74hcs137dr.step / sn74hcs137dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (26 pp, sha256 aabb655d9da421b4, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF