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MSP430F5255IRGCR
Public Made by Adomby adom
Texas Instruments Microcontrollers (MCU/MPU/SOC), VQFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownMSP430F5255IRGCR
Texas Instruments · Microcontrollers (MCU/MPU/SOC) · VQFN-64-EP(9x9)
MSP430F5255IRGCR from Texas Instruments, in a VQFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P6.0/TA2CLK/SMCLK/CB0/A0 | bidirectional | General-purpose I/O on the DVCC domain with port interrupt, also TA2 clock input, SMCLK output, Comparator_B input CB0 and ADC analog input A0. |
| 2 | P6.1/TA2.0/CB1/A1 | bidirectional | General-purpose I/O on the DVCC domain with port interrupt, also TA2 CCR0 capture/compare output, Comparator_B input CB1, ADC analog input A1 and BSL transmit output. |
| 3 | P6.2/TA2.1/CB2/A2 | bidirectional | General-purpose I/O on the DVCC domain with port interrupt, also TA2 CCR1 capture/compare output, Comparator_B input CB2, ADC analog input A2 and BSL receive input. |
| 4 | P6.3/TA2.2/CB3/A3 | bidirectional | General-purpose I/O on the DVCC domain with port interrupt, also TA2 CCR2 capture/compare output, Comparator_B input CB3 and ADC analog input A3. |
| 5 | P6.4/CB4/A4 | bidirectional | General-purpose I/O on the DVCC domain with port interrupt, also Comparator_B input CB4 and ADC analog input A4. |
| 6 | P6.5/CB5/A5 | bidirectional | General-purpose I/O on the DVCC domain with port interrupt, also Comparator_B input CB5 and ADC analog input A5. |
| 7 | P6.6/CB6/A6 | bidirectional | General-purpose I/O on the DVCC domain with port interrupt, also Comparator_B input CB6 and ADC analog input A6. |
| 8 | P6.7/CB7/A7 | bidirectional | General-purpose I/O on the DVCC domain with port interrupt, also Comparator_B input CB7 and ADC analog input A7. |
| 9 | P5.0/A8/VeREF+ | bidirectional | General-purpose I/O on the DVCC domain, also ADC analog input A8 and external ADC reference voltage input VeREF+ (not available on all device types). |
| 10 | P5.1/A9/VeREF- | bidirectional | General-purpose I/O on the DVCC domain, also ADC analog input A9 and negative terminal for an externally applied ADC reference voltage VeREF- (not available on all device types). |
| 11 | AVCC | power_in | Analog power supply. |
| 12 | P5.4/XIN | bidirectional | General-purpose I/O on the DVCC domain, also input terminal for crystal oscillator XT1 (in bypass mode XIN can take a digital waveform from DVSS to DVCC or DVSS to DVIO). |
| 13 | P5.5/XOUT | bidirectional | General-purpose I/O on the DVCC domain, also output terminal of crystal oscillator XT1. |
| 14 | AVSS | power_in | Analog ground supply. |
| 15 | DVCC | power_in | Digital power supply. |
| 16 | DVSS | power_in | Digital ground supply. |
| 17 | VCORE | power_out | Regulated core power supply output for internal use only; no external current loading is possible and only the recommended capacitor CVCORE should be connected. |
| 18 | P1.0/TA0CLK/ACLK | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA0 clock input and ACLK output (divided by 1, 2, 4, 8, 16 or 32). |
| 19 | P1.1/TA0.0 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA0 CCR0 capture input CCI0A and compare output Out0. |
| 20 | P1.2/TA0.1 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA0 CCR1 capture input CCI1A and compare output Out1. |
| 21 | P1.3/TA0.2 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA0 CCR2 capture input CCI2A and compare output Out2. |
| 22 | P1.4/TA0.3 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA0 CCR3 capture input CCI3A and compare output Out3. |
| 23 | P1.5/TA0.4 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA0 CCR4 capture input CCI4A and compare output Out4. |
| 24 | P1.6/TA1CLK/CBOUT | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA1 clock input and Comparator_B output. |
| 25 | P1.7/TA1.0 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA1 CCR0 capture input CCI0A and compare output Out0. |
| 26 | P2.0/TA1.1 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA1 CCR1 capture input CCI1A and compare output Out1. |
| 27 | P2.1/TA1.2 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also TA1 CCR2 capture input CCI2A and compare output Out2. |
| 28 | P2.2/UCB3SIMO/UCB3SDA | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also USCI_B3 SPI slave-in/master-out or I2C data (USCI_B3). |
| 29 | P2.3/UCB3SOMI/UCB3SCL | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also USCI_B3 SPI slave-out/master-in or I2C clock (USCI_B3). |
| 30 | P2.4/UCB3CLK/UCA3STE | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also USCI_B3 SPI clock input (slave) or output (master) and USCI_A3 SPI slave transmit enable. |
| 31 | P2.5/UCB3STE/UCA3CLK | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also USCI_B3 SPI slave transmit enable and USCI_A3 SPI clock input (slave) or output (master). |
| 32 | P2.6/RTCCLK/DMAE0 | bidirectional | General-purpose I/O on the DVIO domain with port interrupt, also RTC clock output for calibration and DMA external trigger input. |
| 33 | P2.7/UCB0STE/UCA0CLK | bidirectional | General-purpose I/O on the DVIO domain, also USCI_B0 SPI slave transmit enable and USCI_A0 SPI clock input (slave) or output (master). |
| 34 | P3.0/UCB0SIMO/UCB0SDA | bidirectional | General-purpose I/O on the DVIO domain, also USCI_B0 SPI slave-in/master-out or I2C data. |
| 35 | P3.1/UCB0SOMI/UCB0SCL | bidirectional | General-purpose I/O on the DVIO domain, also USCI_B0 SPI slave-out/master-in or I2C clock. |
| 36 | P3.2/UCB0CLK/UCA0STE | bidirectional | General-purpose I/O on the DVIO domain, also USCI_B0 SPI clock input (slave) or output (master) and USCI_A0 SPI slave transmit enable. |
| 37 | P3.3/UCA0TXD/UCA0SIMO | bidirectional | General-purpose I/O on the DVIO domain, also USCI_A0 UART transmit data or SPI slave-in/master-out. |
| 38 | P3.4/UCA0RXD/UCA0SOMI | bidirectional | General-purpose I/O on the DVIO domain, also USCI_A0 UART receive data or SPI slave-out/master-in. |
| 39 | DVSS | power_in | Digital ground supply for the DVIO domain. |
| 40 | DVIO | power_in | Digital I/O power supply for the DVIO domain; the voltage on DVIO is not supervised or monitored. |
| 41 | P4.0/PM_UCB1STE/PM_UCA1CLK | bidirectional | General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_B1 SPI slave transmit enable or USCI_A1 clock input/output. |
| 42 | P4.1/PM_UCB1SIMO/PM_UCB1SDA | bidirectional | General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-in/master-out or I2C data. |
| 43 | P4.2/PM_UCB1SOMI/PM_UCB1SCL | bidirectional | General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_B1 SPI slave-out/master-in or I2C clock. |
| 44 | P4.3/PM_UCB1CLK/PM_UCA1STE | bidirectional | General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_B1 SPI clock or USCI_A1 SPI slave transmit enable. |
| 45 | P4.4/PM_UCA1TXD/PM_UCA1SIMO | bidirectional | General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_A1 UART transmit data or SPI slave-in/master-out. |
| 46 | P4.5/PM_UCA1RXD/PM_UCA1SOMI | bidirectional | General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_A1 UART receive data or SPI slave-out/master-in. |
| 47 | P4.6/PM_UCA3TXD/PM_UCA3SIMO | bidirectional | General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_A3 UART transmit data or SPI slave-in/master-out. |
| 48 | P4.7/PM_UCA3RXD/PM_UCA3SOMI | bidirectional | General-purpose I/O on the DVIO domain with reconfigurable port mapping; default mapping is USCI_A3 UART receive data or SPI slave-out/master-in. |
| 49 | P7.0/UCA2TXD/UCA2SIMO | bidirectional | General-purpose I/O on the DVIO domain, also USCI_A2 UART transmit data or SPI slave-in/master-out. |
| 50 | P7.1/UCA2RXD/UCA2SOMI | bidirectional | General-purpose I/O on the DVIO domain, also USCI_A2 UART receive data or SPI slave-out/master-in. |
| 51 | P7.2/UCB2CLK/UCA2STE | bidirectional | General-purpose I/O on the DVIO domain, also USCI_B2 SPI clock input (slave) or output (master) and USCI_A2 SPI slave transmit enable. |
| 52 | P7.3/UCB2SIMO/UCB2SDA | bidirectional | General-purpose I/O on the DVIO domain, also USCI_B2 SPI slave-in/master-out or I2C data. |
| 53 | P7.4/UCB2SOMI/UCB2SCL | bidirectional | General-purpose I/O on the DVIO domain, also USCI_B2 SPI slave-out/master-in or I2C clock. |
| 54 | P7.5/UCB2STE/UCA2CLK | bidirectional | General-purpose I/O on the DVIO domain, also USCI_B2 SPI slave transmit enable and USCI_A2 SPI clock input (slave) or output (master). |
| 55 | BSLEN | input | BSL enable input on the DVIO domain with internal pulldown; used together with RST/NMI for the DVIO-domain bootloader entry sequence. |
| 56 | RST/NMI | input | Active-low reset input or nonmaskable interrupt input on the DVIO domain; when driven externally, input swing from DVSS to DVIO is required and the internal pullup is enabled by default when configured as reset. |
| 57 | P5.2/XT2IN | bidirectional | General-purpose I/O on the DVCC domain, also input terminal for crystal oscillator XT2 (in bypass mode it can take a digital waveform from DVSS to DVCC or DVSS to DVIO). |
| 58 | P5.3/XT2OUT | bidirectional | General-purpose I/O on the DVCC domain, also output terminal of crystal oscillator XT2. |
| 59 | TEST/SBWTCK | input | Test mode pin that selects four-wire JTAG operation on the DVCC domain, and Spy-Bi-Wire input clock when Spy-Bi-Wire is active. |
| 60 | PJ.0/TDO | bidirectional | General-purpose I/O on the DVCC domain, also JTAG test data output port. |
| 61 | PJ.1/TDI/TCLK | bidirectional | General-purpose I/O on the DVCC domain, also JTAG test data input or test clock input. |
| 62 | PJ.2/TMS | bidirectional | General-purpose I/O on the DVCC domain, also JTAG test mode select. |
| 63 | PJ.3/TCK | bidirectional | General-purpose I/O on the DVCC domain, also JTAG test clock. |
| 64 | RSTDVCC/SBWTDIO | bidirectional | Nonconfigurable active-low reset input on the DVCC domain with internal pullup to DVCC (external drive requires swing from DVSS to DVCC), also Spy-Bi-Wire data input/output. |
| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-64-EP(9x9) |
| Category | Embedded Processors & Controllers |
| Pins | 65 |
CAD (KiCad official)
- Symbol:
MSP430F5255IRGCR - Footprint:
Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm - 3D model: VQFN-64-EP(9x9) (KiCad packages3D, STEP)
- 3D model files:
msp430f5255irgcr-etched.step/msp430f5255irgcr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);msp430f5255irgcr.step/msp430f5255irgcr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (112 pp, sha256
52c9555dc979ab2f, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).