AD5662BRJZ-2REEL7 from Analog Devices, in a SOT-23-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD	power_in	Power supply input that can be operated from 2.7 V to 5.5 V and should be decoupled to GND.
2	VREF	power_in	Reference voltage input that the DAC requires to set its output range; the datasheet gives a reference input range of 0.75 V to VDD.
3	VFB	input	Feedback connection for the output amplifier that should be connected to VOUT for normal operation.
4	VOUT	output	Analog output voltage from the DAC, driven by an output amplifier with rail-to-rail operation.
5	SYNC	input	Level-triggered active-low frame synchronization input that enables the input shift register; the DAC updates after the 24th clock unless SYNC is taken high first, in which case the rising edge aborts the write.
6	SCLK	input	Serial clock input on which data is clocked into the input shift register on the falling edge, at rates up to 30 MHz.
7	DIN	input	Serial data input to a 24-bit shift register, clocked in on the falling edge of the serial clock.
8	GND	power_in	Ground reference point for all circuitry on the part.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SOT-23-8
Category	ADC/DAC/Data Conversion
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Relative Accuracy (INL), B grade	INL	-16	8	16	LSB		3
Differential Nonlinearity, B grade	DNL	-1		1	LSB	Guaranteed monotonic by design	3
Zero Code Error, B grade			2	10	mV	All 0s loaded to DAC register	3
Full-Scale Error, B grade		-1	-0.2		% FSR	All 1s loaded to DAC register	3
Offset Error, B grade		-10		10	mV		3
Gain Error, B grade		-1.5		1.5	% FSR		3
Zero Code Error Drift, B grade		-2		2	μV/°C	Guaranteed by design and characterization	3
Gain Temperature Coefficient, B grade		-2.5		2.5	ppm Of FSR/°C	Guaranteed by design and characterization	3
DC Power Supply Rejection Ratio, B grade	PSRR			-100	dB	DAC code = midscale; VDD = 5 V/3 V ±10%	3
Output Voltage Range (lower limit)	VOUT	0			V	Upper limit printed as VDD	3
Output Voltage Settling Time, B grade			8	10	μs	¼ to ¾ scale change settling to ±2 LSB; RL = 2 kΩ; 0 pF < CL < 200 pF	3
Reference Current	IREF		40	75	μA	VREF = VDD = 5 V	3
Reference Current	IREF		30	50	μA	VREF = VDD = 3.6 V	3
Input Current	IIN	-2		2	μA	All digital inputs	3
Input Low Voltage	VINL			0.8	V	VDD = 5 V, 3 V	3
Input High Voltage	VINH	2			V	VDD = 5 V, 3 V	3
Power Supply Voltage	VDD	2.7		5.5	V	All digital inputs at 0 V or VDD	4
Normal Mode Supply Current	IDD		150	250	μA	DAC active, excluding load current; VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND	4
Normal Mode Supply Current	IDD		140	225	μA	DAC active, excluding load current; VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND	4
All Power-Down Modes Supply Current	IDD		0.48	1	μA	VDD = 4.5 V to 5.5 V; VIH = VDD and VIL = GND	4
All Power-Down Modes Supply Current	IDD		0.1	0.375	μA	VDD = 2.7 V to 3.6 V; VIH = VDD and VIL = GND	4
SCLK cycle time	t1	50			ns	VDD = 2.7 V to 3.6 V	5
SCLK cycle time	t1	33			ns	VDD = 3.6 V to 5.5 V	5
SCLK high time	t2	13			ns	VDD = 2.7 V to 5.5 V	5
SCLK low time	t3	13			ns	VDD = 2.7 V to 5.5 V	5
SYNC to SCLK falling edge setup time	t4	13			ns	VDD = 2.7 V to 5.5 V	5
Data setup time	t5	5			ns	VDD = 2.7 V to 5.5 V	5
Data hold time	t6	4.5			ns	VDD = 2.7 V to 5.5 V	5
SCLK falling edge to SYNC rising edge	t7	0			ns	VDD = 2.7 V to 5.5 V	5
Minimum SYNC high time	t8	50			ns	VDD = 2.7 V to 3.6 V	5
Minimum SYNC high time	t8	33			ns	VDD = 3.6 V to 5.5 V	5
SYNC rising edge to SCLK fall ignore	t9	13			ns	VDD = 2.7 V to 5.5 V	5
SCLK falling edge to SYNC fall ignore	t10	0			ns	VDD = 2.7 V to 5.5 V	5
VDD to GND	VDD	-0.3		7	V	TA = 25°C	6
VOUT to GND	VOUT	-0.3			V	TA = 25°C; upper limit printed as VDD + 0.3 V	6
VFB to GND	VFB	-0.3			V	TA = 25°C; upper limit printed as VDD + 0.3 V	6
VREF to GND	VREF	-0.3			V	TA = 25°C; upper limit printed as VDD + 0.3 V	6
Digital Input Voltage to GND		-0.3			V	TA = 25°C; upper limit printed as VDD + 0.3 V	6
Operating Temperature Range (Y version)	TA	-40		125	°C		6
Storage Temperature Range	TSTG	-65		150	°C		6
Junction Temperature (TJ max)	TJ			150	°C		6
Reflow Soldering Peak Temperature, Pb-free				260	°C	Pb-free	6
ESD				2	kV		6
Thermal Impedance, junction-to-ambient	θJA		119		°C/W	SOT-23 package, 4-layer board	6

CAD (KiCad official)

Symbol: AD5662BRJZ-2REEL7
Footprint: Package_TO_SOT_SMD:SOT-23-8
3D model: SOT-23-8 (KiCad packages3D, STEP)
3D model files: ad5662brjz-2reel7-etched.step / ad5662brjz-2reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad5662brjz-2reel7.step / ad5662brjz-2reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (24 pp, sha256 3f3377bce3423dc9, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD5662BRJZ-2REEL7

Verified AD5662BRJZ-2REEL7

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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