component
SN74AC11N
Public Made by Adomby adom
Texas Instruments Logic Gates, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownSN74AC11N
Texas Instruments · Logic Gates · PDIP-14
SN74AC11N from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1 input A of the three-input AND gate; the input voltage range is 0 V to VCC per the recommended operating conditions. |
| 2 | 1B | input | Channel 1 input B of the three-input AND gate; the input voltage range is 0 V to VCC per the recommended operating conditions. |
| 3 | 2A | input | Channel 2 input A of the three-input AND gate; the input voltage range is 0 V to VCC per the recommended operating conditions. |
| 4 | 2B | input | Channel 2 input B of the three-input AND gate; the input voltage range is 0 V to VCC per the recommended operating conditions. |
| 5 | 2C | input | Channel 2 input C of the three-input AND gate; the input voltage range is 0 V to VCC per the recommended operating conditions. |
| 6 | 2Y | output | Channel 2 AND-gate output Y (Y = A·B·C); the output voltage range is 0 V to VCC and IOL/IOH are limited to ±24 mA at VCC = 4.5 V to 5.5 V. |
| 7 | GND | power_in | Ground reference for the device. |
| 8 | 3Y | output | Channel 3 AND-gate output Y (Y = A·B·C); the output voltage range is 0 V to VCC and IOL/IOH are limited to ±24 mA at VCC = 4.5 V to 5.5 V. |
| 9 | 3C | input | Channel 3 input of the three-input AND gate; the input voltage range is 0 V to VCC. The pin table text labels this pin as 'Input A', which conflicts with the pin name 3C. |
| 10 | 3B | input | Channel 3 input B of the three-input AND gate; the input voltage range is 0 V to VCC per the recommended operating conditions. |
| 11 | 3A | input | Channel 3 input of the three-input AND gate; the input voltage range is 0 V to VCC. The pin table text labels this pin as 'Input C', which conflicts with the pin name 3A. |
| 12 | 1Y | output | Channel 1 AND-gate output Y (Y = A·B·C); the output voltage range is 0 V to VCC and IOL/IOH are limited to ±24 mA at VCC = 4.5 V to 5.5 V. |
| 13 | 1C | input | Channel 1 input C of the three-input AND gate; the input voltage range is 0 V to VCC per the recommended operating conditions. |
| 14 | VCC | power_in | Positive supply; the recommended supply range is 2 V to 6 V (absolute maximum 7 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | PDIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 2 | 6 | V | 5 | ||
| High-level input voltage | VIH | 2.1 | V | VCC = 3V | 5 | ||
| High-level input voltage | VIH | 3.15 | V | VCC = 4.5V | 5 | ||
| High-level input voltage | VIH | 3.85 | V | VCC = 5.5V | 5 | ||
| Low-level input voltage | VIL | 0.9 | V | VCC = 3V | 5 | ||
| Low-level input voltage | VIL | 1.35 | V | VCC = 4.5V | 5 | ||
| Low-level input voltage | VIL | 1.65 | V | VCC = 5.5V | 5 | ||
| Input voltage | VI | 0 | V | upper limit printed as VCC | 5 | ||
| Output voltage | VO | 0 | V | upper limit printed as VCC | 5 | ||
| High-level output current | IOH | -12 | mA | VCC = 3V | 5 | ||
| High-level output current | IOH | -24 | mA | VCC = 4.5V | 5 | ||
| Low-level output current | IOL | 12 | mA | VCC = 3V | 5 | ||
| Low-level output current | IOL | 24 | mA | VCC = 4.5V | 5 | ||
| Input transition rise or fall rate | Δt/Δv | 8 | ns/V | 5 | |||
| Operating free-air temperature | TA | -40 | 85 | °C | SN74AC11 (commercial) | 5 | |
| Supply voltage range | VCC | -0.5 | 7 | V | 5 | ||
| Input voltage range | VI | -0.5 | V | upper limit printed as VCC + 0.5 | 5 | ||
| Output voltage range | VO | -0.5 | V | upper limit printed as VCC + 0.5 | 5 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < 0 or VI > VCC | 5 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < 0 or VO > VCC | 5 | |
| Continuous output current | IO | -50 | 50 | mA | VO = 0 or VCC | 5 | |
| Continuous current through VCC or GND | -200 | 200 | mA | 5 | |||
| Storage temperature range | Tstg | -65 | 150 | °C | 5 | ||
| Junction-to-ambient thermal resistance | RθJA | 80 | °C/W | N (PDIP, 14 pins) package | 6 | ||
| High-level output voltage | VOH | 2.9 | 2.99 | V | IOH = -50 µA, VCC = 3V | 6 | |
| High-level output voltage | VOH | 4.4 | 4.49 | V | IOH = -50 µA, VCC = 4.5V | 6 | |
| High-level output voltage | VOH | 5.4 | 5.49 | V | IOH = -50 µA, VCC = 5.5V | 6 | |
| High-level output voltage | VOH | 2.46 | 2.56 | V | IOH = -12 mA, VCC = 3V | 6 | |
| High-level output voltage | VOH | 3.76 | 3.86 | V | IOH = -24 mA, VCC = 4.5V | 6 | |
| High-level output voltage | VOH | 4.76 | 4.86 | V | IOH = -24 mA, VCC = 5.5V | 6 | |
| Low-level output voltage | VOL | 0.002 | 0.1 | V | IOL = 50 µA, VCC = 3V | 6 | |
| Low-level output voltage | VOL | 0.001 | 0.1 | V | IOL = 50 µA, VCC = 4.5V | 6 | |
| Low-level output voltage | VOL | 0.36 | 0.44 | V | IOL = 12 mA, VCC = 3V | 6 | |
| Input current | II | -1 | 1 | µA | VI = VCC or GND, VCC = 5.5V | 6 | |
| Quiescent supply current | ICC | 2 | 20 | µA | VI = VCC or GND, IO = 0, VCC = 5.5V | 6 | |
| Propagation delay low-to-high (A, B or C to Y) | tPLH | 1 | 5.5 | 10 | ns | VCC = 3.3V ± 0.3V; see Load Circuit | 6 |
| Propagation delay high-to-low (A, B or C to Y) | tPHL | 1 | 5.5 | 9.5 | ns | VCC = 3.3V ± 0.3V; see Load Circuit | 6 |
| Propagation delay low-to-high (A, B or C to Y) | tPLH | 1 | 4 | 8.5 | ns | VCC = 5V ± 0.5V; see Load Circuit | 7 |
| Propagation delay high-to-low (A, B or C to Y) | tPHL | 1 | 4 | 7.5 | ns | VCC = 5V ± 0.5V; see Load Circuit | 7 |
CAD (KiCad official)
- Symbol:
SN74AC11N - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74ac11n-etched.step/sn74ac11n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74ac11n.step/sn74ac11n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (38 pp, sha256
0dc64ee9baca2d3e, retrieved 2026-10-16, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).