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Contents

README

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TPS651851RSLR

Texas Instruments · Global Sourcing Parts · VQFN-48-EP(6x6)

TPS651851RSLR from Texas Instruments, in a VQFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREF power_in Filter pin for 2.25-V internal reference voltage to ADC; connect a 4.7-µF capacitor from this pin to ground.
2 INT output Open-drain interrupt pin (active low); pulled low when one or more INT1 or INT2 bits are set.
3 VNEG power_out Negative supply output pin for panel source drivers at -15V nominal; connect a 4.7-µF capacitor from this pin to ground.
4 VNEG_IN power_in Input pin for LDO2 (VNEG) from DCDC2 output in range 15.2-16.8V; connect a 4.7-µF capacitor from this pin to ground.
5 WAKEUP input Wake-up pin (active high); pull this pin high to wake up from sleep mode and enable I2C interface.
6 DGND power_in Digital ground reference point; connect to ground plane.
7 INT_LDO output Filter pin for 2.7-V internal supply; connect a 4.7-µF capacitor from this pin to ground.
8 AGND1 power_in Analog ground for general analog circuitry and VCOM driver circuit reference.
9 VNEG_DIS output Discharge pin for VNEG output rail; connect to VNEG to enable active discharge when rail is disabled.
10 VIN power_in Input power supply to general circuitry in range 3-6V; connect a 10-µF capacitor from this pin to ground.
11 N/C unconnected Not internally connected; leave floating.
12 VCOM_CTRL input VCOM amplifier enable control pin; pull high to enable or tie to battery for automatic sequencing with power rails.
13 N/C unconnected Not internally connected; leave floating.
14 VCOM_DIS input Discharge pin for VCOM output; connect to ground to discharge VCOM when disabled or leave floating if not desired.
15 VCOM output Filter pin for panel common-voltage driver output in range 0V to -5.11V with 10mV resolution; connect a 4.7-µF capacitor from this pin to ground.
16 VCOM_PWR power_in Internal supply input pin to VCOM buffer; connect to DCDC2 output and add 4.7-µF capacitor from this pin to ground.
17 SCL input I2C serial interface clock input; supports 100-400 kHz clock frequency with 0.4V input low threshold.
18 SDA bidirectional I2C serial interface data input/output (open-drain); requires external pull-up resistor with output low threshold of 0.4V.
19 VPOS_DIS input Discharge pin for VPOS output; connect resistor from VPOS_DIS to VPOS to discharge when rail disabled or leave floating if not desired.
20 N/C unconnected Not internally connected; leave floating.
21 PWRUP input Power-up pin (edge-sensitive); pull high to transition from STANDBY to ACTIVE mode and power up output rails.
22 PBKG passive Die substrate connection; connect to VN pin (-16V) with short wide trace to improve heat dissipation.
23 PWR_GOOD output Open-drain power-good output pin; pulled low when any of four power rails (CP1, CP2, LDO1, LDO2) are disabled or not in regulation.
24 VIN_P power_in Input power supply to inverting buck-boost converter (DCDC2) in range 3-6V; connect a 10-µF capacitor from this pin to ground.
25 VN_SW output Inverting buck-boost converter (DCDC2) switch output; connects to external inductor for -16V generation.
26 VN power_in Feedback pin for inverting buck-boost converter (DCDC2) at -16V output and supply for VNEG LDO and VEE charge pump; connect 4.7-µF capacitor from this pin to ground.
27 VEE_IN power_in Input supply pin for negative charge pump (CP2); connect output of VN buck-boost converter at -16V.
28 VEE_DRV output Driver output pin for negative charge pump (CP2) generating -20V rail with 15mA output current capability for TPS651851.
29 VEE_DIS input Discharge pin for VEE output rail; connect resistor from VEE_DIS to VEE to enable active discharge when disabled or leave floating if not desired.
30 VEE_D output Base voltage output pin for negative charge pump (CP2); connect a 100-nF capacitor from this pin to ground.
31 VEE_FB input Feedback pin for negative charge pump (CP2) with typical feedback voltage of -0.994V at -20V output.
32 PGND2 power_in Power ground for CP1 (VDDH) and CP2 (VEE) charge pumps; provides return path for pump currents.
33 VDDH_FB input Feedback pin for positive charge pump (CP1) with typical feedback voltage of 0.998V at 22V output.
34 VDDH_D output Base voltage output pin for positive charge pump (CP1); connect a 100-nF capacitor from this pin to ground.
35 VDDH_DIS input Discharge pin for VDDH output rail; connect to VDDH to discharge when rail disabled or leave floating if not desired.
36 VDDH_DRV output Driver output pin for positive charge pump (CP1) generating 22V rail with 15mA output current capability for TPS651851.
37 VDDH_IN power_in Input supply pin for positive charge pump (CP1); connect output of VB boost converter at +16V.
38 N/C unconnected Not internally connected; leave floating.
39 N/C unconnected Not internally connected; leave floating.
40 VB_SW output Boost converter (DCDC1) switch output; connects to external inductor for +16V generation.
41 PGND1 power_in Power ground for DCDC1 boost converter; provides return path for boost converter current.
42 VB power_in Feedback pin for boost converter (DCDC1) at +16V output and supply for VPOS LDO and VDDH charge pump; connect 4.7-µF capacitor from this pin to ground.
43 VPOS_IN power_in Input pin for LDO1 (VPOS) from DCDC1 output in range 15.2-16.8V; connect a 4.7-µF capacitor from this pin to ground.
44 VPOS power_out Positive supply output pin for panel source drivers at +15V nominal; connect a 4.7-µF capacitor from this pin to ground.
45 VIN3P3 power_in Input pin to 3.3-V power switch in range 3-6V; connect to system 3.3V supply that requires gating to E-Ink panel.
46 V3P3 power_out Output pin of integrated 3.3-V power switch; provides gated 3.3V supply to E-Ink display panel with 10Ω on-resistance.
47 TS input Thermistor input pin for panel temperature monitoring; connect 10-kΩ NTC thermistor and 43-kΩ linearization resistor between this pin and AGND2.
48 AGND2 power_in Reference ground point for external thermistor and linearization resistor; measures panel temperature from -10°C to 85°C.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(6x6)
Category Global Sourcing Parts
Pins 49

CAD (KiCad official)

  • Symbol: TPS651851RSLR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: VQFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tps651851rslr-etched.step / tps651851rslr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tps651851rslr.step / tps651851rslr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (66 pp, sha256 903effae4b79ef29, retrieved 2026-10-01, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF