SN65LVDS1050PWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1B	input	Receiver 1 inverting differential (LVDS) input B, with a 100-mV minimum differential threshold and a -0.5 V to 4 V voltage range.
2	1A	input	Receiver 1 non-inverting differential (LVDS) input A, with a 100-mV minimum differential threshold and a -0.5 V to 4 V voltage range.
3	1R	tri_state	Receiver 1 logic output, high-impedance when RE is high, with VOH of 2 V min at -8 mA and VOL of 0.4 V max at 8 mA.
4	RE	input	Receiver enable input (LVTTL, 5-V tolerant) that puts the receiver outputs in high impedance when high.
5	2R	tri_state	Receiver 2 logic output, high-impedance when RE is high, with VOH of 2 V min at -8 mA and VOL of 0.4 V max at 8 mA.
6	2A	input	Receiver 2 non-inverting differential (LVDS) input A, with a 100-mV minimum differential threshold and a -0.5 V to 4 V voltage range.
7	2B	input	Receiver 2 inverting differential (LVDS) input B, with a 100-mV minimum differential threshold and a -0.5 V to 4 V voltage range.
8	GND	power_in	Ground, the reference terminal for all voltage values except differential I/O bus voltages.
9	2D	input	Driver 2 logic input (LVTTL, 5-V tolerant) with VIH of 2 V min and VIL of 0.8 V max.
10	2Y	tri_state	Driver 2 non-inverting LVDS output, high-impedance when DE is low, with a typical 285-mV differential output into 100 Ω.
11	2Z	tri_state	Driver 2 inverting LVDS output, high-impedance when DE is low, with a typical 285-mV differential output into 100 Ω.
12	DE	input	Driver enable input (LVTTL, 5-V tolerant) that enables the driver outputs when high and puts them in high impedance when low.
13	1Z	tri_state	Driver 1 inverting LVDS output, high-impedance when DE is low, with a typical 285-mV differential output into 100 Ω.
14	1Y	tri_state	Driver 1 non-inverting LVDS output, high-impedance when DE is low, with a typical 285-mV differential output into 100 Ω.
15	1D	input	Driver 1 logic input (LVTTL, 5-V tolerant) with VIH of 2 V min and VIL of 0.8 V max.
16	VCC	power_in	Supply voltage pin, operating from 2.4 V to 3.6 V with an absolute maximum of 4 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	TSSOP-16
Category	Interface
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage	VCC	-0.5		4	V		3
Voltage range (D, R, DE, RE)		-0.5		6	V		3
Voltage range (Y, Z, A, B)		-0.5		4	V		3
Storage temperature range		-65		150	°C		3
Lead temperature				250	°C	1,6 mm (1/16 inch) from case for 10 seconds	3
Supply voltage	VCC	2.4	2.7	3.6	V		3
High-level input voltage	VIH	2			V		3
Low-level input voltage	VIL			0.8	V		3
Magnitude of differential input voltage	/VID/	0.1		0.6	V		3
Driver output voltage	VOY or VOZ	0		2.4	V		3
Magnitude of differential output voltage with disabled driver	/VOD(dis)/			520	mV		3
Common-mode input voltage	VIC	0			V	see Figure 5; upper limit printed as VCC-0.8	3
Operating free-air temperature	TA	-40		85	°C		3
Power rating				774	mW	TA≤25°C, package PW	3
Power rating				402	mW	TA=85°C, package PW	3
Derating factor			6.2		mW/°C	package PW, as printed in dissipation rating table	3
Supply current, driver and receiver enabled	ICC		12	20	mA	No receiver load, Driver RL=100 Ω	3
Supply current, driver enabled, receiver disabled	ICC		10	16	mA	RL=100 Ω	3
Supply current, driver disabled, receiver enabled	ICC		3	6	mA	No load	3
Supply current, disabled	ICC		0.5	1	mA	Disabled	3
Differential output voltage magnitude	/VOD/	247	285	454	mV	RL=100Ω, See Figure 1 and Figure 2	4
Change in differential output voltage magnitude between logic states	Δ/VOD/			50	mV		4
Steady-state common-mode output voltage	VOC(SS)	1.125		1.37	V	See Figure 3	4
Change in steady-state common-mode output voltage between logic states	ΔVOC(SS)			50	mV	See Figure 3	4
Peak-to-peak common-mode output voltage	VOC(PP)		50	150	mV	See Figure 3	4
High-level input current (DE)	IIH		0.5	20	µA	VIH=5 V	4
High-level input current (D)	IIH		2	20	µA	VIH=5 V	4
Low-level input current (DE)	IIL		0.5	10	µA	VIL=0.8 V	4
Low-level input current (D)	IIL		2	20	µA	VIL=0.8 V	4
Short-circuit output current	IOS		3	10	mA	VOY or VOZ=0 V	4
Off-state output current	IO(OFF)	-1		1	µA	DE=0 V, VOY=VOZ=0 V; DE=VCC, VOY=VOZ=0 V, VCC < 1.5 V	4
Input capacitance	CIN		3		pF		4
Positive-going differential input voltage threshold	VITH+			100	mV	See Figure 5 and Table 1	4
Negative-going differential input voltage threshold	VITH-			100	mV	See Figure 5 and Table 1	4
High-level output voltage	VOH	2			V	IOH=-8 mA	4
Low-level output voltage	VOL			0.4	V	IOL=8 mA	4
Input current (A or B inputs)	II		2	20	µA	VI=0	4
Input current (A or B inputs)	II		1.2		µA	VI=2.4 V	4
Power-off input current (A or B inputs)	II(OFF)	-20		20	µA	VCC=0	4
High-level input current (enables)	IIH	-10		10	µA	VIH=5 V	4
Low-level input current (enables)	IIL	-10		10	µA	VIL=0.8 V	4
High-impedance output current	IOZ	-10		10	µA	VO=0 or 5 V	4
Pulse skew (/tPHL - tPLH/) driver	tsk(p)			300	ps	RL=100Ω, CL=10 pF, See Figure 2	5
Channel-to-channel output skew	tsk(o)			150	ps	RL=100Ω, CL=10 pF, See Figure 2	5
Driver enable time	ten		7.8	10	ns	See Figure 4	5
Driver disable time	tdis		6.6	10	ns	See Figure 4	5
Propagation delay time, high-to-low-level output (driver)	tPHL		1.7	3	ns	RL=100Ω, CL=10 pF, See Figure 2	5
Propagation delay time, low-to-high-level output (driver)	tPLH		1.7		ns	RL=100Ω, CL=10 pF, See Figure 2	5
Differential output signal rise time	tr		0.8	1	ns	RL=100Ω, CL=10 pF, See Figure 2	5
Differential output signal fall time	tf		0.8	1	ns	RL=100Ω, CL=10 pF, See Figure 2	5
Propagation delay time, low-to-high-level output (receiver)	tPLH		3.7	5.2	ns	CL=10 pF, See Figure 6	5
Propagation delay time, high-to-low-level output (receiver)	tPHL		3.7	4.5	ns	CL=10 pF, See Figure 6	5
Pulse skew (/tPHL - tPLH/) receiver	tsk(p)		0.3		ns	CL=10 pF, See Figure 6	5
Output signal rise time (receiver)	tr		0.8	1.5	ns	CL=10 pF, See Figure 6	5
Output signal fall time (receiver)	tf		0.8	1.5	ns	CL=10 pF, See Figure 6	5
Propagation delay time, high-level-to-high-impedance output	tPZH		5.4		ns	See Figure 7	5
Propagation delay time, low-level-to-low-impedance output	tPZL		6.3		ns	See Figure 7	5
Propagation delay time, high-impedance-to-high-level output	tPHZ		6.1		ns	See Figure 7	5
Propagation delay time, low-impedance-to-high-level output	tPLZ		6.9		ns	See Figure 7	5

CAD (KiCad official)

Symbol: SN65LVDS1050PWR
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: sn65lvds1050pwr-etched.step / sn65lvds1050pwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); sn65lvds1050pwr.step / sn65lvds1050pwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (24 pp, sha256 716440531aeb2564, retrieved 2026-11-06, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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SN65LVDS1050PWR

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