component
SN74HCS11QPWRQ1
Public Made by Adomby adom
Texas Instruments Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HCS11QPWRQ1
Texas Instruments · Gates · TSSOP-14
SN74HCS11QPWRQ1 from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Channel 1 input A of the 3-input AND gate with Schmitt-trigger input; unused inputs must be tied to VCC or GND. |
| 2 | 1B | input | Channel 1 input B of the 3-input AND gate with Schmitt-trigger input; unused inputs must be tied to VCC or GND. |
| 3 | 2A | input | Channel 2 input A of the 3-input AND gate with Schmitt-trigger input; unused inputs must be tied to VCC or GND. |
| 4 | 2B | input | Channel 2 input B of the 3-input AND gate with Schmitt-trigger input; unused inputs must be tied to VCC or GND. |
| 5 | 2C | input | Channel 2 input C of the 3-input AND gate with Schmitt-trigger input; unused inputs must be tied to VCC or GND. |
| 6 | 2Y | output | Channel 2 output Y (Y = A·B·C), balanced CMOS push-pull output with ±7.8mA drive at 5V that may be left floating if unused. |
| 7 | GND | power_in | Ground pin. |
| 8 | 3Y | output | Channel 3 output Y (Y = A·B·C), balanced CMOS push-pull output with ±7.8mA drive at 5V that may be left floating if unused. |
| 9 | 3A | input | Channel 3 input A of the 3-input AND gate with Schmitt-trigger input; unused inputs must be tied to VCC or GND. |
| 10 | 3B | input | Channel 3 input B of the 3-input AND gate with Schmitt-trigger input; unused inputs must be tied to VCC or GND. |
| 11 | 3C | input | Channel 3 input C of the 3-input AND gate with Schmitt-trigger input; unused inputs must be tied to VCC or GND. |
| 12 | 1Y | output | Channel 1 output Y (Y = A·B·C), balanced CMOS push-pull output with ±7.8mA drive at 5V that may be left floating if unused. |
| 13 | 1C | input | Channel 1 input C of the 3-input AND gate with Schmitt-trigger input; unused inputs must be tied to VCC or GND. |
| 14 | VCC | power_in | Positive supply, recommended range 2V to 6V (absolute max 7V), with a 0.1µF bypass capacitor placed close to the pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive switching threshold | VT+ | 1.13 | 1.26 | 1.37 | V | VCC = 2V | 5 |
| Positive switching threshold | VT+ | 2.31 | 2.47 | 2.66 | V | VCC = 4.5V | 5 |
| Positive switching threshold | VT+ | 2.99 | 3.18 | 3.44 | V | VCC = 6V | 5 |
| Negative switching threshold | VT- | 0.55 | 0.62 | 0.71 | V | VCC = 2V | 5 |
| Negative switching threshold | VT- | 1.21 | 1.36 | 1.5 | V | VCC = 4.5V | 5 |
| Negative switching threshold | VT- | 1.56 | 1.79 | 1.99 | V | VCC = 6V | 5 |
| Hysteresis VT+ - VT- | ΔVT | 0.54 | 0.64 | 0.71 | V | VCC = 2V | 5 |
| Hysteresis VT+ - VT- | ΔVT | 0.94 | 1.11 | 1.27 | V | VCC = 4.5V | 5 |
| Hysteresis VT+ - VT- | ΔVT | 1.2 | 1.38 | 1.57 | V | VCC = 6V | 5 |
| High-level output voltage | VOH | -0.1 | -0.002 | V | VI = VIH or VIL, IOH = -20µA, VCC = 2V to 6V (printed as VCC - 0.1 min, VCC - 0.002 typ) | 5 | |
| High-level output voltage | VOH | 4 | 4.3 | V | VI = VIH or VIL, IOH = -6mA, VCC = 4.5V | 5 | |
| High-level output voltage | VOH | 5.4 | 5.75 | V | VI = VIH or VIL, IOH = -7.8mA, VCC = 6V | 5 | |
| Low-level output voltage | VOL | 0.002 | 0.1 | V | VI = VIH or VIL, IOL = 20µA, VCC = 2V to 6V | 5 | |
| Low-level output voltage | VOL | 0.18 | 0.3 | V | VI = VIH or VIL, IOL = 4mA, VCC = 4.5V | 5 | |
| Low-level output voltage | VOL | 0.22 | 0.33 | V | VI = VIH or VIL, IOL = 7.8mA, VCC = 6V | 5 | |
| Input leakage current | II | 100 | 1000 | nA | VI = VCC or 0, VCC = 6V (typ ±100, max ±1000) | 5 | |
| Supply current | ICC | 0.1 | 2 | µA | VI = VCC or 0, IO = 0, VCC = 6V | 5 | |
| Input capacitance | Ci | 5 | pF | VCC = 2V to 6V | 5 | ||
| Power dissipation capacitance per gate | Cpd | 10 | pF | No load, VCC = 2V to 6V | 5 | ||
| Propagation delay A/B/C to Y | tpd | 13 | 40 | ns | VCC = 2V | 5 | |
| Propagation delay A/B/C to Y | tpd | 6 | 17 | ns | VCC = 4.5V | 5 | |
| Propagation delay A/B/C to Y | tpd | 5 | 16 | ns | VCC = 6V | 5 | |
| Transition time | tt | 9 | 17 | ns | VCC = 2V | 5 | |
| Transition time | tt | 5 | 8 | ns | VCC = 4.5V | 5 | |
| Transition time | tt | 4 | 7 | ns | VCC = 6V | 5 | |
| Supply voltage | VCC | 2 | 5 | 6 | V | 4 | |
| Input voltage | VI | 0 | 6 | V | 0 to VCC | 4 | |
| Output voltage | VO | 0 | 6 | V | 0 to VCC | 4 | |
| Ambient temperature | TA | -40 | 125 | °C | 4 | ||
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Input clamp current | IIK | -20 | 20 | mA | VI < -0.5 or VI > VCC + 0.5 | 4 | |
| Output clamp current | IOK | -20 | 20 | mA | VO < -0.5 or VO > VCC + 0.5 | 4 | |
| Continuous output current | IO | -35 | 35 | mA | VO = 0 to VCC | 4 | |
| Continuous current through VCC or GND | -70 | 70 | mA | 4 | |||
| Junction temperature | TJ | 150 | °C | 4 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| ESD HBM | V(ESD) | -4000 | 4000 | V | HBM per AEC Q100-002, classification level 2 | 4 | |
| ESD CDM | V(ESD) | -1500 | 1500 | V | CDM per AEC Q100-011, classification level C6 | 4 | |
| Junction-to-ambient thermal resistance | RθJA | 151.7 | °C/W | PW (TSSOP) 14 pin | 4 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 79.4 | °C/W | PW (TSSOP) 14 pin | 4 | ||
| Junction-to-board thermal resistance | RθJB | 94.7 | °C/W | PW (TSSOP) 14 pin | 4 | ||
| Junction-to-top characterization parameter | ΨJT | 25.2 | °C/W | PW (TSSOP) 14 pin | 4 | ||
| Junction-to-board characterization parameter | ΨJB | 94.1 | °C/W | PW (TSSOP) 14 pin | 4 |
CAD (KiCad official)
- Symbol:
SN74HCS11QPWRQ1 - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74hcs11qpwrq1-etched.step/sn74hcs11qpwrq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hcs11qpwrq1.step/sn74hcs11qpwrq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (25 pp, sha256
ab7bf165451501e5, retrieved 2026-10-26, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).