component
LM25117PMHE
Public Made by Adomby adom
Texas Instruments Current-Sensing Amplifiers, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM25117PMHE
Texas Instruments · Current-Sensing Amplifiers · HTSSOP-20-EP
LM25117PMHE from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | UVLO | input | Undervoltage lockout enable pin; regulator disabled below 0.4V, in standby mode (VCC on, HO/LO outputs off) from 0.4V to 1.25V, and operates normally above 1.25V with 20 µA hysteresis sink current. |
| 2 | DEMB | input | Diode emulation mode enable input; active low with internal 50 kΩ pull-down; enables diode emulation when low or floating to prevent reverse current through low-side NMOS; disabled (continuous conduction) when high. |
| 3 | RES | passive | Restart timer pin for discontinuous mode current limiting; external capacitor determines standby duration before automatic restart; 10 µA sink current charges capacitor to 1.25V threshold. |
| 4 | SS | passive | Soft-start voltage ramp pin; external capacitor charged by 10 µA sink current controls error amplifier ramp slope and output voltage rise time; held low when VCC < 4V, UVLO < 1.25V, or during thermal shutdown. |
| 5 | RT | passive | Oscillator timing resistor pin; switching frequency set by resistor between RT and AGND; accepts external clock synchronization via AC-coupled positive edge pulses up to 750 kHz. |
| 6 | AGND | power_in | Analog ground return; common reference for 0.8V internal voltage reference circuit and all analog signal circuits. |
| 7 | VCCDIS | input | VCC regulator disable input; internal VCC regulator disabled when above 1.25V threshold to enable external bias supply; has 500 kΩ internal pull-down resistor for normal operation when floating. |
| 8 | FB | input | Feedback input to error amplifier; external resistor divider sets output voltage regulation point with 0.8V internal reference. |
| 9 | COMP | output | Compensated error signal output from error amplifier; loop compensation network connects between this pin and FB pin for frequency response shaping. |
| 10 | CM | output | Current monitor output; provides voltage proportional to average inductor current with approximately 20.5 V/V gain; connect directly to AGND with optional RC filter for bandwidth limiting. |
| 11 | RAMP | passive | PWM ramp slope compensation node; external resistor connected between SW and RAMP and external capacitor between RAMP and AGND generate ramp signal proportional to inductor current for slope compensation. |
| 12 | CS | input | Current sense amplifier high-side input; connects to high side of external current sense resistor for cycle-by-cycle current limiting with 10 V/V gain. |
| 13 | CSG | power_in | Current sense Kelvin ground connection; direct connection to low side of current sense resistor for minimal offset error in current sensing. |
| 14 | PGND | power_in | Power ground return for low-side NMOS gate driver; direct connection to current sense resistor low side and low-side MOSFET source. |
| 15 | LO | output | Low-side NMOS gate driver output; peak source/sink current ±3.3A via short low-inductance path to gate of low-side power MOSFET; output voltage swings between 0V and VCC. |
| 16 | VCC | power_in | Internal bias supply pin; powered by internal 7.6V regulator or optional external supply; requires 0.47-10 µF low-ESR bypass capacitor close to package for local decoupling. |
| 17 | SW | passive | Buck converter power switch node; common connection point between source of high-side NMOS and drain of low-side NMOS; sensed internally for ramp generation and bootstrap capacitor charging. |
| 18 | HO | output | High-side NMOS gate driver output; peak source/sink current ±3.3A from bootstrap supply HB via short low-inductance path to gate of high-side power MOSFET. |
| 19 | HB | power_in | High-side gate driver bootstrap supply node; charged from VCC through external bootstrap diode when low-side NMOS is on; supplies 0.1 µF minimum bootstrap capacitor. |
| 20 | VIN | power_in | Main power supply input; supplies internal VCC regulator with input voltage range 4.5V to 42V; requires low-ESR bypass capacitor and optional RC filter for noise suppression. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Operational Amplifier/Comparator |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
LM25117PMHE - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
lm25117pmhe-etched.step/lm25117pmhe-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm25117pmhe.step/lm25117pmhe.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
ebaf723e350b87ed, retrieved 2026-10-07, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).