component
74HCT174D
Public Made by Adomby adom
Nexperia Flip Flops, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdown74HCT174D
Nexperia · Flip Flops · SO-16
74HCT174D from Nexperia, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Asynchronous master reset input, active LOW; a LOW level resets all flip-flops and Qn outputs to LOW regardless of CP. |
| 2 | Q0 | output | Flip-flop 0 output; it follows the stored D0 value on the LOW-to-HIGH clock transition and is forced LOW by MR. |
| 3 | D0 | input | Data input for flip-flop 0; the level must meet the set-up and hold times to CP (4.5 V: tsu 12 ns, th 3 ns at 25 °C per Table 7). |
| 4 | D1 | input | Data input for flip-flop 1; the level must meet the set-up and hold times to CP referenced in Table 7. |
| 5 | Q1 | output | Flip-flop 1 output; it follows the stored D1 value on the LOW-to-HIGH clock transition and is forced LOW by MR. |
| 6 | D2 | input | Data input for flip-flop 2; the level must meet the set-up and hold times to CP referenced in Table 7. |
| 7 | Q2 | output | Flip-flop 2 output; it follows the stored D2 value on the LOW-to-HIGH clock transition and is forced LOW by MR. |
| 8 | GND | power_in | Ground (0 V) reference for all voltages on the device. |
| 9 | CP | input | Clock input, LOW-to-HIGH edge-triggered; all six D inputs are loaded simultaneously on this edge. |
| 10 | Q3 | output | Flip-flop 3 output; it follows the stored D3 value on the LOW-to-HIGH clock transition and is forced LOW by MR. |
| 11 | D3 | input | Data input for flip-flop 3; the level must meet the set-up and hold times to CP referenced in Table 7. |
| 12 | Q4 | output | Flip-flop 4 output; it follows the stored D4 value on the LOW-to-HIGH clock transition and is forced LOW by MR. |
| 13 | D4 | input | Data input for flip-flop 4; the level must meet the set-up and hold times to CP referenced in Table 7. |
| 14 | D5 | input | Data input for flip-flop 5; the level must meet the set-up and hold times to CP referenced in Table 7. |
| 15 | Q5 | output | Flip-flop 5 output; it follows the stored D5 value on the LOW-to-HIGH clock transition and is forced LOW by MR. |
| 16 | VCC | power_in | Positive supply voltage; 2.0 V to 6.0 V for 74HC174 and 4.5 V to 5.5 V for 74HCT174 per the recommended operating conditions. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Nexperia |
| Package | SO-16 |
| Category | Logic |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input clamping current | IIK | -20 | 20 | mA | VI < -0.5 V or VI > VCC + 0.5 V | 3 | |
| Output clamping current | IOK | -20 | 20 | mA | VO < -0.5 V or VO > VCC + 0.5 V | 3 | |
| Output current | IO | -25 | 25 | mA | -0.5 V < VO < VCC + 0.5 V | 3 | |
| Supply current | ICC | 50 | mA | 3 | |||
| Ground current | IGND | -50 | mA | 3 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| Total power dissipation | Ptot | 500 | mW | Tamb = -40 °C to +125 °C | 3 | ||
| Supply voltage | VCC | -0.5 | 7 | V | 3 | ||
| Supply voltage (74HCT174) | VCC | 4.5 | 5 | 5.5 | V | 74HCT174 column | 4 |
| Input voltage | VI | 0 | V | 4 | |||
| Output voltage | VO | 0 | V | 4 | |||
| Ambient temperature | Tamb | -40 | 125 | °C | 4 | ||
| Input transition rise and fall rate | Δt/ΔV | 1.67 | 139 | ns/V | VCC = 4.5 V | 4 | |
| HIGH-level input voltage | VIH | 2 | 1.6 | V | VCC = 4.5 V to 5.5 V; 25 °C | 5 | |
| HIGH-level input voltage | VIH | 2 | V | VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 5 | ||
| LOW-level input voltage | VIL | 1.2 | 0.8 | V | VCC = 4.5 V to 5.5 V; 25 °C | 5 | |
| LOW-level input voltage | VIL | 0.8 | V | VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 5 | ||
| HIGH-level output voltage | VOH | 4.4 | 4.5 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; 25 °C | 5 | |
| HIGH-level output voltage | VOH | 4.4 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -20 μA; -40 °C to +85 °C | 5 | ||
| HIGH-level output voltage | VOH | 3.98 | 4.32 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; 25 °C | 5 | |
| HIGH-level output voltage | VOH | 3.84 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; -40 °C to +85 °C | 5 | ||
| HIGH-level output voltage | VOH | 3.7 | V | VI = VIH or VIL; VCC = 4.5 V; IO = -4.0 mA; -40 °C to +125 °C | 5 | ||
| LOW-level output voltage | VOL | 0 | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; 25 °C | 5 | |
| LOW-level output voltage | VOL | 0.1 | V | VI = VIH or VIL; VCC = 4.5 V; IO = 20 μA; -40 °C to +85 °C | 5 | ||
| LOW-level output voltage | VOL | 0.15 | 0.26 | V | VI = VIH or VIL; VCC = 5.5 V; IO = 5.2 mA; 25 °C | 5 | |
| LOW-level output voltage | VOL | 0.33 | V | VI = VIH or VIL; VCC = 5.5 V; IO = 5.2 mA; -40 °C to +85 °C | 5 | ||
| LOW-level output voltage | VOL | 0.4 | V | VI = VIH or VIL; VCC = 5.5 V; IO = 5.2 mA; -40 °C to +125 °C | 5 | ||
| Input leakage current | II | -0.1 | 0.1 | μA | VI = VCC or GND; VCC = 5.5 V; 25 °C | 5 | |
| Input leakage current | II | -1 | 1 | μA | VI = VCC or GND; VCC = 5.5 V; -40 °C to +85 °C | 5 | |
| Supply current | ICC | 8 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; 25 °C | 5 | ||
| Supply current | ICC | 80 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +85 °C | 5 | ||
| Supply current | ICC | 160 | μA | VI = VCC or GND; IO = 0 A; VCC = 5.5 V; -40 °C to +125 °C | 5 | ||
| Additional supply current, Dn input | ΔICC | 25 | 90 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; 25 °C | 5 | |
| Additional supply current, Dn input | ΔICC | 112.5 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 5 | ||
| Additional supply current, Dn input | ΔICC | 122.5 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 5 | ||
| Additional supply current, CP input | ΔICC | 130 | 468 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; 25 °C | 5 | |
| Additional supply current, CP input | ΔICC | 585 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 5 | ||
| Additional supply current, CP input | ΔICC | 637 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 5 | ||
| Additional supply current, MR input | ΔICC | 125 | 450 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; 25 °C | 5 | |
| Additional supply current, MR input | ΔICC | 562.5 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +85 °C | 5 | ||
| Additional supply current, MR input | ΔICC | 612.5 | μA | per input pin; VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; -40 °C to +125 °C | 5 | ||
| Propagation delay CP to Qn | tpd | 21 | 35 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 6; 25 °C | 7 | |
| Propagation delay CP to Qn | tpd | 53 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 6; -40 °C to +125 °C | 7 | ||
| HIGH to LOW propagation delay MR to Qn | tPHL | 20 | 35 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 7; 25 °C | 7 | |
| HIGH to LOW propagation delay MR to Qn | tPHL | 53 | ns | VCC = 4.5 V; CL = 50 pF; see Fig. 7; -40 °C to +125 °C | 7 | ||
| Maximum frequency | fmax | 30 | 63 | MHz | VCC = 4.5 V; CP input; see Fig. 6; 25 °C | 7 | |
| Maximum frequency | fmax | 20 | MHz | VCC = 4.5 V; CP input; see Fig. 6; -40 °C to +125 °C | 7 | ||
| Set-up time Dn to CP | tsu | 16 | 4 | ns | VCC = 4.5 V; see Fig. 6; 25 °C | 7 | |
| Set-up time Dn to CP | tsu | 24 | ns | VCC = 4.5 V; see Fig. 6; -40 °C to +125 °C | 7 | ||
| CP pulse width HIGH or LOW | tW | 16 | 7 | ns | VCC = 4.5 V; CP input HIGH or LOW; see Fig. 6; 25 °C | 7 | |
| CP pulse width HIGH or LOW | tW | 24 | ns | VCC = 4.5 V; CP input HIGH or LOW; see Fig. 6; -40 °C to +125 °C | 7 | ||
| MR pulse width LOW | tW | 20 | 7 | ns | VCC = 4.5 V; MR input LOW; see Fig. 7; 25 °C | 7 | |
| MR pulse width LOW | tW | 30 | ns | VCC = 4.5 V; MR input LOW; see Fig. 7; -40 °C to +125 °C | 7 | ||
| Hold time Dn to CP | th | 5 | -3 | ns | VCC = 4.5 V; see Fig. 6; 25 °C | 7 | |
| Recovery time MR to CP | trec | 12 | -3 | ns | VCC = 4.5 V; MR to CP; see Fig. 7; 25 °C | 7 |
CAD (KiCad official)
- Symbol:
74HCT174D - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files:
74hct174d-etched.step/74hct174d-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);74hct174d.step/74hct174d.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Nexperia datasheet (14 pp, sha256
0dbc19171a4bbd3c, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).