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CKS32F407VET6

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CKS Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerscks32f407vet6factory-2.0.0extractor-text
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Contents

README

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CKS32F407VET6

CKS · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

CKS32F407VET6 from CKS, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5 V-tolerant (FT) I/O with alternate functions TRACECLK, FSMC_A23, ETH_MII_TXD3 and EVENTOUT, floating input during and after reset.
2 PE3 bidirectional 5 V-tolerant (FT) I/O with alternate functions TRACE0, FSMC_A19 and EVENTOUT, floating input during and after reset.
3 PE4 bidirectional 5 V-tolerant (FT) I/O with alternate functions TRACE1, FSMC_A20, DCMI_D4 and EVENTOUT, floating input during and after reset.
4 PE5 bidirectional 5 V-tolerant (FT) I/O with alternate functions TRACE2, FSMC_A21, TIM9_CH1, DCMI_D6 and EVENTOUT, floating input during and after reset.
5 PE6 bidirectional 5 V-tolerant (FT) I/O with alternate functions TRACE3, FSMC_A22, TIM9_CH2, DCMI_D7 and EVENTOUT, floating input during and after reset.
6 VBAT power_in Backup-domain supply of 1.65 to 3.6 V that powers the RTC, backup registers and backup SRAM when VDD is absent, and must not be left floating.
7 PC13 bidirectional Power-switched 5 V-tolerant I/O (RTC_OUT, RTC_TAMP1, RTC_TS, EVENTOUT) whose output use is limited to a 3 mA sink/source, a maximum of 2 MHz at 30 pF, and no current-source use such as driving LEDs.
8 PC14 bidirectional Power-switched I/O that serves as the OSC32_IN input for the 32.768 kHz low-speed crystal, with the same output limits of 3 mA, 2 MHz and 30 pF.
9 PC15 bidirectional Power-switched I/O that serves as the OSC32_OUT output for the 32.768 kHz low-speed crystal, with the same output limits of 3 mA, 2 MHz and 30 pF.
10 VSS power_in Ground reference for the digital I/O and core supply, which must be connected to the external supply system.
11 VDD power_in Digital supply of 1.8 to 3.6 V that powers the I/O pins and the internal voltage regulator.
12 PH0 bidirectional 5 V-tolerant I/O that serves as the OSC_IN input of the 4 to 26 MHz high-speed crystal oscillator, also with EVENTOUT.
13 PH1 bidirectional 5 V-tolerant I/O that serves as the OSC_OUT output of the 4 to 26 MHz high-speed crystal oscillator, also with EVENTOUT.
14 NRST bidirectional Bidirectional active-low reset pin with an internal weak pull-up of 30 to 50 kΩ, and the datasheet recommends a 0.1 µF filter capacitor.
15 PC0 bidirectional 5 V-tolerant I/O with ADC123_IN10 analog input and alternate functions OTG_HS_ULPI_STP and EVENTOUT.
16 PC1 bidirectional 5 V-tolerant I/O with ADC123_IN11 analog input and alternate functions ETH_MDC and EVENTOUT.
17 PC2 bidirectional 5 V-tolerant I/O with ADC123_IN12 analog input and alternate functions SPI2_MISO, OTG_HS_ULPI_DIR, ETH_MII_TXD2, I2S2ext_SD and EVENTOUT.
18 PC3 bidirectional 5 V-tolerant I/O with ADC123_IN13 analog input and alternate functions SPI2_MOSI, I2S2_SD, OTG_HS_ULPI_NXT, ETH_MII_TX_CLK and EVENTOUT.
19 VDD power_in Digital supply of 1.8 to 3.6 V that powers the I/O pins and the internal voltage regulator.
20 VSSA power_in Analog ground for the ADC, DAC, reset block, RC oscillators and PLL, which must be connected to VSS.
21 VREF+ power_in Positive reference voltage for the ADC and DAC, where the datasheet requires VDDA − VREF+ < 1.2 V.
22 VDDA power_in Analog supply of 1.8 to 3.6 V for the ADC, DAC, reset block, RC oscillators and PLL, which must be connected to VDD and is recommended to be at the same supply with at most 300 mV difference.
23 PA0 bidirectional 5 V-tolerant I/O that also serves as the WKUP wake-up pin and ADC123_IN0 analog input, with alternate functions USART2_CTS, UART4_TX, TIM2_CH1_ETR, TIM5_CH1, TIM8_ETR and EVENTOUT.
24 PA1 bidirectional 5 V-tolerant I/O with ADC123_IN1 analog input and alternate functions USART2_RTS, UART4_RX, ETH_RMII_REF_CLK, TIM5_CH2, TIM2_CH2 and EVENTOUT.
25 PA2 bidirectional 5 V-tolerant I/O with ADC123_IN2 analog input and alternate functions USART2_TX, TIM5_CH3, TIM9_CH1, TIM2_CH3, ETH_MDIO and EVENTOUT.
26 PA3 bidirectional 5 V-tolerant I/O with ADC123_IN3 analog input and alternate functions USART2_RX, TIM5_CH4, TIM9_CH2, TIM2_CH4, OTG_HS_ULPI_D0 and ETH_MII_COL.
27 VSS power_in Ground pin that must be connected to the external supply system.
28 VDD power_in Digital supply of 1.8 to 3.6 V that powers the I/O pins and the internal voltage regulator.
29 PA4 bidirectional 3.3 V-tolerant TTa I/O connected directly to the ADC with DAC_OUT1 and ADC12_IN4 analog functions, plus alternate functions SPI1_NSS, SPI3_NSS, USART2_CK, DCMI_HSYNC, OTG_HS_SOF and I2S3_WS.
30 PA5 bidirectional 3.3 V-tolerant TTa I/O connected directly to the ADC with DAC_OUT2 and ADC12_IN5 analog functions, plus alternate functions SPI1_SCK, OTG_HS_ULPI_CK, TIM2_CH1_ETR and TIM8_CH1N.
31 PA6 bidirectional 5 V-tolerant I/O with ADC12_IN6 analog input and alternate functions SPI1_MISO, TIM8_BKIN, TIM13_CH1, DCMI_PIXCLK, TIM3_CH1 and TIM1_BKIN.
32 PA7 bidirectional 5 V-tolerant I/O with ADC12_IN7 analog input and alternate functions SPI1_MOSI, TIM8_CH1N, TIM14_CH1, TIM3_CH2, ETH_MII_RX_DV, TIM1_CH1N and ETH_RMII_CRS_DV.
33 PC4 bidirectional 5 V-tolerant I/O with ADC12_IN14 analog input and alternate functions ETH_RMII_RX_D0 and ETH_MII_RX_D0.
34 PC5 bidirectional 5 V-tolerant I/O with ADC12_IN15 analog input and alternate functions ETH_RMII_RX_D1 and ETH_MII_RX_D1.
35 PB0 bidirectional 5 V-tolerant I/O with ADC12_IN8 analog input and alternate functions TIM3_CH3, TIM8_CH2N, OTG_HS_ULPI_D1, ETH_MII_RXD2 and TIM1_CH2N.
36 PB1 bidirectional 5 V-tolerant I/O with ADC12_IN9 analog input and alternate functions TIM3_CH4, TIM8_CH3N, OTG_HS_ULPI_D2, ETH_MII_RXD3 and TIM1_CH3N.
37 PB2/BOOT1 bidirectional 5 V-tolerant I/O that is shared with the BOOT1 boot-mode function and has EVENTOUT as its alternate function.
38 PE7 bidirectional 5 V-tolerant I/O with alternate functions FSMC_D4, TIM1_ETR and EVENTOUT.
39 PE8 bidirectional 5 V-tolerant I/O with alternate functions FSMC_D5, TIM1_CH1N and EVENTOUT.
40 PE9 bidirectional 5 V-tolerant I/O with alternate functions FSMC_D6, TIM1_CH1 and EVENTOUT.
41 PE10 bidirectional 5 V-tolerant I/O with alternate functions FSMC_D7, TIM1_CH2N and EVENTOUT.
42 PE11 bidirectional 5 V-tolerant I/O with alternate functions FSMC_D8, TIM1_CH2 and EVENTOUT.
43 PE12 bidirectional 5 V-tolerant I/O with alternate functions FSMC_D9, TIM1_CH3N and EVENTOUT.
44 PE13 bidirectional 5 V-tolerant I/O with alternate functions FSMC_D10, TIM1_CH3 and EVENTOUT.
45 PE14 bidirectional 5 V-tolerant I/O with alternate functions FSMC_D11, TIM1_CH4 and EVENTOUT.
46 PE15 bidirectional 5 V-tolerant I/O with alternate functions FSMC_D12, TIM1_BKIN and EVENTOUT.
47 PB10 bidirectional 5 V-tolerant I/O with alternate functions SPI2_SCK, I2S2_CK, I2C2_SCL, USART3_TX, OTG_HS_ULPI_D3, ETH_MII_RX_ER and TIM2_CH3.
48 PB11 bidirectional 5 V-tolerant I/O with alternate functions I2C2_SDA, USART3_RX, OTG_HS_ULPI_D4, ETH_MII_TX_EN, ETH_RMII_TX_EN and TIM2_CH4.
49 VCAP_1 power_out Internal regulator decoupling pin that requires an external 2.2 µF capacitor with ESR below 2 Ω, or two 100 nF capacitors when the regulator is off.
50 VDD power_in Digital supply of 1.8 to 3.6 V that powers the I/O pins and the internal voltage regulator.
51 PB12 bidirectional 5 V-tolerant I/O with alternate functions SPI2_NSS, I2S2_WS, I2C2_SMBA, USART3_CK, TIM1_BKIN, CAN2_RX, OTG_HS_ULPI_D5, ETH_RMII_TXD0 and OTG_HS_ID.
52 PB13 bidirectional 5 V-tolerant I/O with alternate functions SPI2_SCK, I2S2_CK, USART3_CTS, TIM1_CH1N, CAN2_TX, OTG_HS_ULPI_D6 and ETH_RMII_TXD1, and also used as OTG_HS_VBUS.
53 PB14 bidirectional 5 V-tolerant I/O with alternate functions SPI2_MISO, TIM1_CH2N, TIM12_CH1, OTG_HS_DM, USART3_RTS, TIM8_CH2N and I2S2ext_SD.
54 PB15 bidirectional 5 V-tolerant I/O with alternate functions SPI2_MOSI, I2S2_SD, TIM1_CH3N, TIM8_CH3N, TIM12_CH2 and OTG_HS_DP, and also used as RTC_REFIN.
55 PD8 bidirectional 5 V-tolerant I/O with alternate functions FSMC_D13, USART3_TX and EVENTOUT.
56 PD9 bidirectional 5 V-tolerant I/O with alternate functions FSMC_D14, USART3_RX and EVENTOUT.
57 PD10 bidirectional 5 V-tolerant I/O with alternate functions FSMC_D15, USART3_CK and EVENTOUT.
58 PD11 bidirectional 5 V-tolerant I/O with alternate functions FSMC_CLE, FSMC_A16, USART3_CTS and EVENTOUT.
59 PD12 bidirectional 5 V-tolerant I/O with alternate functions FSMC_ALE, FSMC_A17, TIM4_CH1, USART3_RTS and EVENTOUT.
60 PD13 bidirectional 5 V-tolerant I/O with alternate functions FSMC_A18, TIM4_CH2 and EVENTOUT.
61 PD14 bidirectional 5 V-tolerant I/O with alternate functions FSMC_D0, TIM4_CH3 and EVENTOUT.
62 PD15 bidirectional 5 V-tolerant I/O with alternate functions FSMC_D1, TIM4_CH4 and EVENTOUT.
63 PC6 bidirectional 5 V-tolerant I/O with alternate functions I2S2_MCK, TIM8_CH1, SDIO_D6, USART6_TX, DCMI_D0, TIM3_CH1 and EVENTOUT.
64 PC7 bidirectional 5 V-tolerant I/O with alternate functions I2S3_MCK, TIM8_CH2, SDIO_D7, USART6_RX, DCMI_D1, TIM3_CH2 and EVENTOUT.
65 PC8 bidirectional 5 V-tolerant I/O with alternate functions TIM8_CH3, SDIO_D0, TIM3_CH3, USART6_CK, DCMI_D2 and EVENTOUT.
66 PC9 bidirectional 5 V-tolerant I/O with alternate functions I2S_CKIN, MCO2, TIM8_CH4, SDIO_D1, I2C3_SDA, DCMI_D3, TIM3_CH4 and EVENTOUT.
67 PA8 bidirectional 5 V-tolerant I/O with alternate functions MCO1, USART1_CK, TIM1_CH1, I2C3_SCL, OTG_FS_SOF and EVENTOUT.
68 PA9 bidirectional 5 V-tolerant I/O with alternate functions USART1_TX, TIM1_CH2, I2C3_SMBA, DCMI_D0 and EVENTOUT, and also used as OTG_FS_VBUS.
69 PA10 bidirectional 5 V-tolerant I/O with alternate functions USART1_RX, TIM1_CH3, OTG_FS_ID, DCMI_D1 and EVENTOUT.
70 PA11 bidirectional 5 V-tolerant I/O with alternate functions USART1_CTS, CAN1_RX, TIM1_CH4, OTG_FS_DM and EVENTOUT.
71 PA12 bidirectional 5 V-tolerant I/O with alternate functions USART1_RTS, CAN1_TX, TIM1_ETR, OTG_FS_DP and EVENTOUT.
72 PA13 bidirectional 5 V-tolerant I/O whose alternate function is JTMS-SWDIO for the serial-wire/JTAG debug interface.
73 VCAP_2 power_out Internal regulator decoupling pin that requires an external 2.2 µF capacitor with ESR below 2 Ω, or two 100 nF capacitors when the regulator is off.
74 VSS power_in Ground pin that must be connected to the external supply system.
75 VDD power_in Digital supply of 1.8 to 3.6 V that powers the I/O pins and the internal voltage regulator.
76 PA14 bidirectional 5 V-tolerant I/O whose alternate function is JTCK-SWCLK for the serial-wire/JTAG debug interface.
77 PA15 bidirectional 5 V-tolerant I/O with alternate functions JTDI, SPI3_NSS, I2S3_WS, TIM2_CH1_ETR and SPI1_NSS.
78 PC10 bidirectional 5 V-tolerant I/O with alternate functions SPI3_SCK, I2S3_CK, UART4_TX, SDIO_D2, DCMI_D8 and USART3_TX.
79 PC11 bidirectional 5 V-tolerant I/O with alternate functions UART4_RX, SPI3_MISO, SDIO_D3, DCMI_D4, USART3_RX and I2S3ext_SD.
80 PC12 bidirectional 5 V-tolerant I/O with alternate functions UART5_TX, SDIO_CK, DCMI_D9, SPI3_MOSI, I2S3_SD and USART3_CK.
81 PD0 bidirectional 5 V-tolerant I/O with alternate functions FSMC_D2, CAN1_RX and EVENTOUT.
82 PD1 bidirectional 5 V-tolerant I/O with alternate functions FSMC_D3, CAN1_TX and EVENTOUT.
83 PD2 bidirectional 5 V-tolerant I/O with alternate functions TIM3_ETR, UART5_RX, SDIO_CMD, DCMI_D11 and EVENTOUT.
84 PD3 bidirectional 5 V-tolerant I/O with alternate functions FSMC_CLK, USART2_CTS and EVENTOUT.
85 PD4 bidirectional 5 V-tolerant I/O with alternate functions FSMC_NOE, USART2_RTS and EVENTOUT.
86 PD5 bidirectional 5 V-tolerant I/O with alternate functions FSMC_NWE, USART2_TX and EVENTOUT.
87 PD6 bidirectional 5 V-tolerant I/O with alternate functions FSMC_NWAIT, USART2_RX and EVENTOUT.
88 PD7 bidirectional 5 V-tolerant I/O with alternate functions USART2_CK, FSMC_NE1, FSMC_NCE2 and EVENTOUT.
89 PB3 bidirectional 5 V-tolerant I/O whose alternate functions include JTDO/TRACESWO, SPI3_SCK, I2S3_CK, TIM2_CH2, SPI1_SCK and EVENTOUT.
90 PB4 bidirectional 5 V-tolerant I/O whose alternate functions include NJTRST, SPI3_MISO, TIM3_CH1, SPI1_MISO and I2S3ext_SD.
91 PB5 bidirectional 5 V-tolerant I/O with alternate functions I2C1_SMBA, CAN2_RX, OTG_HS_ULPI_D7, ETH_PPS_OUT, TIM3_CH2, SPI1_MOSI, SPI3_MOSI, DCMI_D10 and I2S3_SD.
92 PB6 bidirectional 5 V-tolerant I/O with alternate functions I2C1_SCL, TIM4_CH1, CAN2_TX, DCMI_D5 and USART1_TX.
93 PB7 bidirectional 5 V-tolerant I/O with alternate functions I2C1_SDA, FSMC_NL, DCMI_VSYNC, USART1_RX and TIM4_CH2.
94 BOOT0 input Boot-mode selection input whose voltage must not exceed 5.5 V.
95 PB8 bidirectional 5 V-tolerant I/O with alternate functions TIM4_CH3, SDIO_D4, TIM10_CH1, DCMI_D6, ETH_MII_TXD3, I2C1_SCL and CAN1_RX.
96 PB9 bidirectional 5 V-tolerant I/O with alternate functions SPI2_NSS, I2S2_WS, TIM4_CH4, TIM11_CH1, SDIO_D5, DCMI_D7, I2C1_SDA and CAN1_TX.
97 PE0 bidirectional 5 V-tolerant I/O with alternate functions TIM4_ETR, FSMC_NBL0, DCMI_D2 and EVENTOUT.
98 PE1 bidirectional 5 V-tolerant I/O with alternate functions FSMC_NBL1, DCMI_D3 and EVENTOUT.
99 VSS power_in Ground pin that must be connected to the external supply system.
100 VDD power_in Digital supply of 1.8 to 3.6 V that powers the I/O pins and the internal voltage regulator.

Key specifications

Parameter Value
Manufacturer CKS
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD for supply and I/O pins (feature list) 1.8 3.6 V 1
ESD voltage, human body model VESD(HBM) 2000 V T = +25 °C，符合 JESD22-A114 72
ESD voltage, charged device model VESD(CDM) 500 V T = +25 °C，符合 ANSI/ESD 72
I/O injection current, BOOT0 pin (negative injection) IINJ 0 mA 73
I/O injection current, NRST pin (negative injection) IINJ 0 mA 73
I/O injection current, PE2..PI7, PDR_ON, BYPASS_REG pins (negative injection) IINJ 0 mA 73
I/O injection current, all FT pins (negative injection) IINJ -5 mA 73
I/O injection current, other pins IINJ -5 5 mA 73
I/O input hysteresis, FT, TTa and NRST pins (footnote 3 minimum) VHYS 200 mV 1.7V≤VDD≤3.6V 74
I/O input hysteresis, BOOT0 pin VHYS 0.1 V 1.75V≤VDD≤3.6V, -40℃≤VDD≤105℃ 74
I/O input leakage current Ilkg -1 1 μA VSS ≤ VIN ≤ VDD 74
I/O FT input leakage current Ilkg 3 μA VIN = 5V 74
Weak pull-up equivalent resistance, all pins except PA10 and PB12 RPU 30 40 50 kΩ VIN = VSS 74
Weak pull-up equivalent resistance, PA10 and PB12 RPU 7 10 14 kΩ 74
Weak pull-down equivalent resistance, all pins except PA10 and PB12 RPD 30 40 50 kΩ VIN = VDD 74
Weak pull-down equivalent resistance, PA10 and PB12 RPD 7 10 14 kΩ 74
GPIO output sink/source current (except PC13 to PC15) -8 8 mA 74
GPIO output sink/source current, PC13 to PC15 -3 3 mA 74
USB OTG FS transceiver startup time tSTARTUP 1 μs 83
USB OTG FS operating voltage VDD 3 3.6 V 83
USB differential input sensitivity VDI 0.2 V I(USB_FS_DP/DM, USB_HS_DP/DM) 83
USB differential common mode range VCM 0.8 2.5 V 包含 VDI 范围 83
USB single-ended receiver threshold VSE 1.3 2 V 83
USB static output low level VOL 0.3 V RL = 1.5kΩ，接到 3.6V 83
USB static output high level VOH 2.8 3.6 V RL = 15kΩ，接到地 83
USB pull-down resistance, PA11, PA12, PB14, PB15 RPD 17 21 24 kΩ VIN=VDD 83
USB pull-down resistance, PA9, PB13 RPD 0.65 1.1 2 kΩ 83
USB pull-up resistance, PA12, PB15 RPU 1.5 1.8 2.1 kΩ VIN=VSS 83
USB pull-up resistance, PA9, PB13 RPU 0.25 0.37 0.55 kΩ 83
USB full-speed rise time tr 4 20 ns CL ≤ 50pF 84
USB full-speed fall time tf 4 20 ns CL ≤ 50pF 84
USB rise/fall time matching tr/tf trfm 90 110 % 84
USB output signal crossover voltage VCRS 1.3 2 V 84
USB OTG HS operating voltage VDD 2.7 3.6 V 84
USB HS clock frequency, first transmission FSTART_8BIT 54 60 66 MHz 8位±10％ 84
USB HS clock frequency, steady state FSTEADY 59.97 60 60.03 MHz ±500ppm 84
USB HS clock duty cycle, first transmission DSTEADY_8BIT 40 50 60 % 8位±10％ 84
USB HS clock duty cycle, steady state DSTEADY 49.975 50 50.025 % ±500ppm 84
Time to reach steady frequency and duty after first transition TSTEADY 1.4 ms 84
Clock start-up time after SuspendM de-assertion, peripheral TSTART_DEV 5.6 ms 外设 84
Ethernet operating voltage VDD 2.7 3.6 V 85
MDC clock frequency (2.38MHz) tMDC 411 420 425 ns 85
SMI write data valid time Td(MDIO) 6 10 13 ns 85
SMI read data setup time tsu(MDIO) 12 ns 85
SMI read data hold time th(MDIO) 0 ns 85
RMII receive data setup time tsu(RXD) 2 ns 86
RMII receive data hold time tih(RXD) 1 ns 86
RMII carrier sense setup time tsu(CRS) 0.5 ns 86
RMII carrier sense hold time tih(CRS) 2 ns 86
RMII transmit enable valid delay td(TXEN) 8 9.5 11 ns 86
RMII transmit data valid delay td(TXD) 8.5 10 11.5 ns 86
ULPI control input setup time (ULPI_DIR) tSC 2 ns VDD = 2.7 V to 3.6 V, TA = -40 to 85°C 84
ULPI control input setup time (ULPI_NXT) tSC 1.5 ns VDD = 2.7 V to 3.6 V, TA = -40 to 85°C 84
ULPI control input hold time (ULPI_DIR, ULPI_NXT) tHC 0 ns VDD = 2.7 V to 3.6 V, TA = -40 to 85°C 84
ULPI data setup time tSD 2 ns VDD = 2.7 V to 3.6 V, TA = -40 to 85°C 84
ULPI data hold time tHD 0 ns VDD = 2.7 V to 3.6 V, TA = -40 to 85°C 84
ULPI control output (ULPI_STP) setup/hold time tDC 9.2 ns VDD = 2.7 V to 3.6 V, TA = -40 to 85°C 85
ULPI data output valid time after clock rising edge tDD 10.7 ns VDD = 2.7 V to 3.6 V, TA = -40 to 85°C 85
I2S slave data output valid time (transmit) tv(SD_ST) 27 从发送（使能边沿后） 82
I/O pin capacitance CIO 5 pF 74

CAD (KiCad official)

  • Symbol: CKS32F407VET6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: cks32f407vet6-etched.step / cks32f407vet6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cks32f407vet6.step / cks32f407vet6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: CKS datasheet (123 pp, sha256 09eb7889abf142f1, retrieved 2026-10-21, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF