component
TPS65320DQPWPRQ1
Public Made by Adomby adom
Texas Instruments Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, HTSSOP-14-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS65320DQPWPRQ1
Texas Instruments · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · HTSSOP-14-EP
TPS65320DQPWPRQ1 from Texas Instruments, in a HTSSOP-14-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOT | output | Bootstrap capacitor node requiring 0.1 µF ceramic capacitor to SW pin; provides bias voltage for high-side MOSFET gate driver. |
| 2 | VIN | power_in | Input power supply for buck regulator internal biasing and high-side MOSFET, operating range 3.6 V to 36 V. |
| 3 | VIN_LDO | power_in | Input power supply for LDO regulator, operating range 3 V to 20 V when in regulation. |
| 4 | LDO_OUT | power_out | Linear regulator output voltage adjustable from 1.1 V to 5.5 V using external feedback resistor divider. |
| 5 | FB2 | input | LDO feedback input pin; connect external resistive divider from LDO_OUT to GND to set output voltage. |
| 6 | nRST | output | Active-low push-pull reset output asserted low when LDO_OUT is below 92% nominal and released high when LDO begins regulating. |
| 7 | EN2 | input | LDO enable input (high-voltage tolerant 40 V); internally pulled to ground; drive high to enable LDO regulator. |
| 8 | EN1 | input | Buck enable input (high-voltage tolerant 40 V); internally pulled to ground; drive high to enable buck regulator. |
| 9 | RT/CLK | input | Timing resistor to ground sets switching frequency (100 kHz to 2.5 MHz) or external clock input for PLL synchronization (300 kHz to 2200 kHz). |
| 10 | SS | input | Soft-start capacitor connection to ground charged by internal 2 µA current source; sets output voltage ramp time from 10% to 90% of final value. |
| 11 | FB1 | input | Buck feedback input pin; connect external resistive divider from buck output to GND to set output voltage range 1.1 V to 20 V. |
| 12 | COMP | output | Error amplifier output and peak-current comparator input; connect frequency compensation network (R and C) to GND. |
| 13 | GND | power_in | Ground reference. |
| 14 | SW | output | Switching node connected to external inductor and catch diode; source of internal high-side MOSFET during conduction. |
| 15 | PowerPAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-14-EP |
| Category | Power Management (PMIC) |
| Pins | 15 |
CAD (KiCad official)
- Symbol:
TPS65320DQPWPRQ1 - Footprint:
Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm - 3D model: HTSSOP-14-EP (KiCad packages3D, STEP)
- 3D model files:
tps65320dqpwprq1-etched.step/tps65320dqpwprq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps65320dqpwprq1.step/tps65320dqpwprq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (45 pp, sha256
44af3b9d372062ba, retrieved 2026-09-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).