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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

LTC2320IUKG-14#PBF

Analog Devices · Analog To Digital Converters (ADCs) · QFN-52-EP(7x8)

LTC2320IUKG-14#PBF from Analog Devices, in a QFN-52-EP(7x8). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AIN6-	input	Analog differential input pin for channel 6; full-scale range (AIN6+ - AIN6-) is ±REFOUT3 voltage; can be driven from VDD to GND.
2	AIN6+	input	Analog differential input pin for channel 6; full-scale range (AIN6+ - AIN6-) is ±REFOUT3 voltage; can be driven from VDD to GND.
3	GND	power_in	Ground; must be tied directly to a solid ground plane.
4	AIN5-	input	Analog differential input pin for channel 5; full-scale range (AIN5+ - AIN5-) is ±REFOUT3 voltage; can be driven from VDD to GND.
5	AIN5+	input	Analog differential input pin for channel 5; full-scale range (AIN5+ - AIN5-) is ±REFOUT3 voltage; can be driven from VDD to GND.
6	REFOUT3	output	Reference buffer 3 output; nominally outputs 4.096V; decouple with 10µF ceramic capacitor to GND; can be overdriven with external reference 1.25V to 5V if REFBUFEN grounded.
7	GND	power_in	Ground; must be tied directly to a solid ground plane.
8	REF	output	Common 4.096V reference output; decouple to GND with 1µF low ESR ceramic capacitor; may be overdriven with single external reference for ADC cores 1-4.
9	REFOUT2	output	Reference buffer 2 output; nominally outputs 4.096V; decouple with 10µF ceramic capacitor to GND; can be overdriven with external reference 1.25V to 5V if REFBUFEN grounded.
10	AIN4-	input	Analog differential input pin for channel 4; full-scale range (AIN4+ - AIN4-) is ±REFOUT2 voltage; can be driven from VDD to GND.
11	AIN4+	input	Analog differential input pin for channel 4; full-scale range (AIN4+ - AIN4-) is ±REFOUT2 voltage; can be driven from VDD to GND.
12	GND	power_in	Ground; must be tied directly to a solid ground plane.
13	AIN3-	input	Analog differential input pin for channel 3; full-scale range (AIN3+ - AIN3-) is ±REFOUT2 voltage; can be driven from VDD to GND.
14	AIN3+	input	Analog differential input pin for channel 3; full-scale range (AIN3+ - AIN3-) is ±REFOUT2 voltage; can be driven from VDD to GND.
15	VDD	power_in	Power supply (3.3V or 5V); bypass to GND with 10µF and 0.1µF ceramic capacitors close to the part; VDD pins must be shorted together and driven from same supply.
16	AIN2-	input	Analog differential input pin for channel 2; full-scale range (AIN2+ - AIN2-) is ±REFOUT1 voltage; can be driven from VDD to GND.
17	AIN2+	input	Analog differential input pin for channel 2; full-scale range (AIN2+ - AIN2-) is ±REFOUT1 voltage; can be driven from VDD to GND.
18	GND	power_in	Ground; must be tied directly to a solid ground plane.
19	AIN1-	input	Analog differential input pin for channel 1; full-scale range (AIN1+ - AIN1-) is ±REFOUT1 voltage; can be driven from VDD to GND.
20	AIN1+	input	Analog differential input pin for channel 1; full-scale range (AIN1+ - AIN1-) is ±REFOUT1 voltage; can be driven from VDD to GND.
21	VDD	power_in	Power supply (3.3V or 5V); bypass to GND with 10µF and 0.1µF ceramic capacitors close to the part; VDD pins must be shorted together and driven from same supply.
22	REFOUT1	output	Reference buffer 1 output; nominally outputs 4.096V; decouple with 10µF ceramic capacitor to GND; can be overdriven with external reference 1.25V to 5V if REFBUFEN grounded.
23	SDR/DDR	input	Double data rate input; controls frequency of SCK and CLKOUT; tie to GND for SDR mode or to OVDD for DDR mode; CLKOUT is delayed version of SCK for both states.
24	CNV	input	Convert input; when high defines acquisition phase; when low initiates conversion and output data readout; must be driven at OVDD levels with low jitter pulse.
25	CMOS/LVDS	input	I/O mode select; ground for CMOS mode, tie to OVDD for LVDS mode, float for low power LVDS mode.
26	GND	power_in	Ground; must be tied directly to a solid ground plane.
27	SDO1	output	CMOS serial data output for ADC channel 1; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data.
28	SDO2	output	CMOS serial data output for ADC channel 2; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data.
29	SDO3	output	CMOS serial data output for ADC channel 3; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data.
30	SDO4	output	CMOS serial data output for ADC channel 4; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data.
31	OVDD	power_in	I/O interface digital power supply (1.71V to 2.63V range); nominally 1.8V or 2.5V for CMOS, 2.5V for LVDS; bypass to GND with 0.1µF capacitor.
32	GND	power_in	Ground; must be tied directly to a solid ground plane.
33	CLKOUT	output	Serial data clock output; provides skew-matched clock to latch SDO output at receiver; echoes SCK input with small delay; logic level determined by OVDD.
34	CLKOUTEN	input	CLKOUT enable control; tie to OVDD to disable CLKOUT for small power savings; ground this pin if CLKOUT is used.
35	SDO5	output	CMOS serial data output for ADC channel 5; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data.
36	SDO6	output	CMOS serial data output for ADC channel 6; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data.
37	OVDD	power_in	I/O interface digital power supply (1.71V to 2.63V range); nominally 1.8V or 2.5V for CMOS, 2.5V for LVDS; bypass to GND with 0.1µF capacitor.
38	GND	power_in	Ground; must be tied directly to a solid ground plane.
39	SDO7	output	CMOS serial data output for ADC channel 7; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data.
40	SDO8	output	CMOS serial data output for ADC channel 8; conversion result shifted MSB first on falling edge of SCK in SDR mode or each SCK edge in DDR mode; 16 SCK edges required for 14-bit data.
41	SCK	input	Serial data clock input; falling edge shifts conversion result MSB first in SDR mode; each edge in DDR mode; logic level determined by OVDD; 100MHz for SDR or 50MHz for DDR at 1.5Msps.
42	DNC	unconnected	Do not connect this pin in CMOS mode.
43	REFBUFEN	input	Reference buffer output enable; tie to VDD when using internal reference; tie to ground to disable internal REFOUT1-4 buffers for external references; has 500kΩ internal pull-up to VDD.
44	VDD	power_in	Power supply (3.3V or 5V); bypass to GND with 10µF and 0.1µF ceramic capacitors close to the part; VDD pins must be shorted together and driven from same supply.
45	REFOUT4	output	Reference buffer 4 output; nominally outputs 4.096V; decouple with 10µF ceramic capacitor to GND; can be overdriven with external reference 1.25V to 5V if REFBUFEN grounded.
46	GND	power_in	Ground; must be tied directly to a solid ground plane.
47	AIN8-	input	Analog differential input pin for channel 8; full-scale range (AIN8+ - AIN8-) is ±REFOUT4 voltage; can be driven from VDD to GND.
48	AIN8+	input	Analog differential input pin for channel 8; full-scale range (AIN8+ - AIN8-) is ±REFOUT4 voltage; can be driven from VDD to GND.
49	GND	power_in	Ground; must be tied directly to a solid ground plane.
50	AIN7-	input	Analog differential input pin for channel 7; full-scale range (AIN7+ - AIN7-) is ±REFOUT4 voltage; can be driven from VDD to GND.
51	AIN7+	input	Analog differential input pin for channel 7; full-scale range (AIN7+ - AIN7-) is ±REFOUT4 voltage; can be driven from VDD to GND.
52	VDD	power_in	Power supply (3.3V or 5V); bypass to GND with 10µF and 0.1µF ceramic capacitors close to the part; VDD pins must be shorted together and driven from same supply.
53	GND	power_in	Exposed pad ground; must be soldered to PCB ground plane.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	QFN-52-EP(7x8)
Category	ADC/DAC/Data Conversion
Pins	53

CAD (KiCad official)

Symbol: LTC2320IUKG-14#PBF
Footprint: Package_DFN_QFN:QFN-52-1EP_7x8mm_P0.5mm_EP5.41x6.45mm
3D model: QFN-52-EP(7x8) (KiCad packages3D, STEP)
3D model files: ltc2320iukg-14-pbf-etched.step / ltc2320iukg-14-pbf-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ltc2320iukg-14-pbf.step / ltc2320iukg-14-pbf.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (34 pp, sha256 321752c03d0fedaf, retrieved 2026-09-17, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF