component
π161U31
Public Made by Adomby adom
2Pai Semi Digital Isolators, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Contents
README
markdownπ161U31
2Pai Semi · Digital Isolators · SOIC-16
π161U31 from 2Pai Semi, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD1 | power_in | Supply voltage for isolator side 1, which operates from 3.0 V to 5.5 V. |
| 2 | VIA | input | Logic input A on side 1; the high-level input must be at least 0.7×VDD1 and the low-level input at most 0.3×VDD1. |
| 3 | VIB | input | Logic input B on side 1; the high-level input must be at least 0.7×VDD1 and the low-level input at most 0.3×VDD1. |
| 4 | VIC | input | Logic input C on side 1; the high-level input must be at least 0.7×VDD1 and the low-level input at most 0.3×VDD1. |
| 5 | VID | input | Logic input D on side 1; the high-level input must be at least 0.7×VDD1 and the low-level input at most 0.3×VDD1. |
| 6 | VIE | input | Logic input E on side 1; the high-level input must be at least 0.7×VDD1 and the low-level input at most 0.3×VDD1. |
| 7 | VOF | output | Logic output F on side 1, with a maximum average output current of ±6 mA (IOH −6 mA, IOL 6 mA). |
| 8 | GND1 | power_in | Ground reference for isolator side 1. |
| 9 | GND2 | power_in | Ground reference for isolator side 2. |
| 10 | VIF | input | Logic input F on side 2; the high-level input must be at least 0.7×VDD2 and the low-level input at most 0.3×VDD2. |
| 11 | VOE | output | Logic output E on side 2, with a maximum average output current of ±6 mA (IOH −6 mA, IOL 6 mA). |
| 12 | VOD | output | Logic output D on side 2, with a maximum average output current of ±6 mA (IOH −6 mA, IOL 6 mA). |
| 13 | VOC | output | Logic output C on side 2, with a maximum average output current of ±6 mA (IOH −6 mA, IOL 6 mA). |
| 14 | VOB | output | Logic output B on side 2, with a maximum average output current of ±6 mA (IOH −6 mA, IOL 6 mA). |
| 15 | VOA | output | Logic output A on side 2, with a maximum average output current of ±6 mA (IOH −6 mA, IOL 6 mA). |
| 16 | VDD2 | power_in | Supply voltage for isolator side 2, which operates from 3.0 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | 2Pai Semi |
| Package | SOIC-16 |
| Category | Interface ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltages (VDD1-GND1, VDD2-GND2) | -0.5 | 7 | V | 4 | |||
| Input Voltages (VIA, VIB); max VDDx + 0.5 V | -0.5 | V | 4 | ||||
| Output Voltages (VOA, VOB); max VDDx + 0.5 V | -0.5 | V | 4 | ||||
| Average Output Current per Pin, Side 1 | IO1 | -10 | 10 | mA | 4 | ||
| Average Output Current per Pin, Side 2 | IO2 | -10 | 10 | mA | 4 | ||
| Common-Mode Transients Immunity | -150 | 150 | kV/µs | See Figure21 for CMTI measurement | 4 | ||
| Storage Temperature (TST) Range | TST | -65 | 150 | °C | 4 | ||
| Supply Voltage | VDDx | 3 | 5.5 | V | 4 | ||
| High Level Input Signal Voltage (min 0.7*VDDx; max VDDx) | VIH | 0.7 | V | 4 | |||
| Low Level Input Signal Voltage (min 0; max 0.3*VDDx) | VIL | 0 | 0.3 | V | 4 | ||
| High Level Output Current | IOH | -6 | mA | 4 | |||
| Low Level Output Current | IOL | 6 | mA | 4 | |||
| Maximum Data Rate | 0 | 150 | Kbps | 4 | |||
| Junction Temperature | TJ | -40 | 150 | °C | 4 | ||
| Ambient Operating Temperature | TA | -40 | 125 | °C | 4 | ||
| Minimum Pulse Width | PW | 6.5 | us | Within pulse width distortion (PWD) limit | 5 | ||
| Propagation Delay Time (tpHL, tpLH) | tpHL, tpLH | 3 | 4.5 | us | 50% input to 50% output @ 5VDC supply | 5 | |
| Propagation Delay Time (tpHL, tpLH) | tpHL, tpLH | 3.2 | 4.8 | us | 50% input to 50% output @ 3.3VDC supply | 5 | |
| Pulse Width Distortion | PWD | 0 | 0.02 | 0.2 | us | @ 5VDC supply; /tpHL - tpLH/ | 5 |
| Part to Part Propagation Delay Skew | tPSK | 0.3 | us | Max difference between any two devices at same temperature, load and voltage; @ 5VDC supply | 5 | ||
| Channel to Channel Propagation Delay Skew | tCSK | 0 | 0.2 | us | Max difference between any two output channels in one device; @ 5VDC supply | 5 | |
| Output Signal Rise/Fall Time | tr/tf | 1.5 | ns | 10% to 90% signal terminated 50 | 5 | ||
| Common-Mode Transient Immunity | CMTI | 100 | 150 | kV/µs | VIN = VDDx2 or 0V, VCM = 1000 V | 5 | |
| ESD (HBM - Human body model) | ESD | -8 | 8 | kV | All pins | 5 | |
| Rising Input Signal Voltage Threshold (min 0.6VDDx; typ 0.7VDDx) | VIT+ | 0.6 | 0.7 | V | 5 | ||
| Falling Input Signal Voltage Threshold (min 0.3VDDx; typ 0.4VDDx) | VIT- | 0.3 | 0.4 | V | 5 | ||
| Low Level Output Voltage | VOL | 0 | 0.1 | V | 20 µA output current | 5 | |
| Low Level Output Voltage | VOL | 0.1 | 0.2 | V | 2 mA output current | 6 | |
| Input Current per Signal Channel | IIN | -10 | 0.5 | 10 | µA | 0 V ≤ Signal voltage ≤ VDDX1 | 6 |
| VDDx1 Undervoltage Rising Threshold | VDDxUV+ | 2.45 | 2.65 | 2.9 | V | 6 | |
| VDDx1 Undervoltage Falling Threshold | VDDxUV− | 2.3 | 2.5 | 2.75 | V | 6 | |
| Rated Dielectric Insulation Voltage (π16xU3x) | 3000 | V rms | 1-minute duration | 7 | |||
| Quiescent Supply Current (π161Uxx @5VDC supply, side 1) | IDD1 (Q) | 536 | 670 | 870 | µA | @ 5VDC Supply; 5V Input signal; CL = 0 pF | 6 |
| Quiescent Supply Current (π161Uxx @5VDC supply, side 2) | IDD2 (Q) | 1949 | 2436 | 3167 | µA | @ 5VDC Supply; 5V Input signal; CL = 0 pF | 6 |
| Quiescent Supply Current (π161Uxx @5VDC supply, side 1) | IDD1 (Q) | 738 | 923 | 1199 | µA | @ 5VDC Supply; 0V Input signal; CL = 0 pF | 6 |
| Quiescent Supply Current (π161Uxx @5VDC supply, side 2) | IDD2 (Q) | 1847 | 2309 | 3002 | µA | @ 5VDC Supply; 0V Input signal; CL = 0 pF | 6 |
| Quiescent Supply Current (π161Uxx @3.3VDC supply, side 1) | IDD1 (Q) | 529 | 662 | 860 | µA | @ 3.3VDC Supply; 3.3V Input signal; CL = 0 pF | 6 |
| Quiescent Supply Current (π161Uxx @3.3VDC supply, side 2) | IDD2 (Q) | 1926 | 2408 | 3130 | µA | @ 3.3VDC Supply; 3.3V Input signal; CL = 0 pF | 6 |
| Quiescent Supply Current (π161Uxx @3.3VDC supply, side 1) | IDD1 (Q) | 630 | 788 | 1024 | µA | @ 3.3VDC Supply; 0V Input signal; CL = 0 pF | 6 |
| Quiescent Supply Current (π161Uxx @3.3VDC supply, side 2) | IDD2 (Q) | 1797 | 2246 | 2920 | µA | @ 3.3VDC Supply; 0V Input signal; CL = 0 pF | 6 |
| Total Supply Current vs Data Throughput (π161Uxx, 2 Kbps, side 1) | IDD1 | 0.79 | 1.18 | mA | @ 5VDC supply; 2 Kbps; CL = 0 pF | 7 | |
| Total Supply Current vs Data Throughput (π161Uxx, 50 Kbps, side 1) | IDD1 | 0.79 | 1.19 | mA | @ 5VDC supply; 50 Kbps; CL = 0 pF | 7 | |
| Total Supply Current vs Data Throughput (π161Uxx, 150 Kbps, side 1) | IDD1 | 0.8 | 1.19 | mA | @ 5VDC supply; 150 Kbps; CL = 0 pF | 7 | |
| Total Supply Current vs Data Throughput (π161Uxx, 2 Kbps, side 2) | IDD2 | 2.37 | 3.56 | mA | @ 5VDC supply; 2 Kbps; CL = 0 pF | 7 | |
| Total Supply Current vs Data Throughput (π161Uxx, 50 Kbps, side 2) | IDD2 | 2.39 | 3.59 | mA | @ 5VDC supply; 50 Kbps; CL = 0 pF | 7 | |
| Total Supply Current vs Data Throughput (π161Uxx, 150 Kbps, side 2) | IDD2 | 2.42 | 3.63 | mA | @ 5VDC supply; 150 Kbps; CL = 0 pF | 7 | |
| Total Supply Current vs Data Throughput (π161Uxx, 2 Kbps, side 1) | IDD1 | 0.71 | 1.06 | mA | @ 3.3VDC supply; 2 Kbps; CL = 0 pF | 7 | |
| Total Supply Current vs Data Throughput (π161Uxx, 50 Kbps, side 1) | IDD1 | 0.71 | 1.07 | mA | @ 3.3VDC supply; 50 Kbps; CL = 0 pF | 7 | |
| Total Supply Current vs Data Throughput (π161Uxx, 150 Kbps, side 1) | IDD1 | 0.71 | 1.07 | mA | @ 3.3VDC supply; 150 Kbps; CL = 0 pF | 7 | |
| Total Supply Current vs Data Throughput (π161Uxx, 2 Kbps, side 2) | IDD2 | 2.33 | 3.5 | mA | @ 3.3VDC supply; 2 Kbps; CL = 0 pF | 7 | |
| Total Supply Current vs Data Throughput (π161Uxx, 50 Kbps, side 2) | IDD2 | 2.33 | 3.5 | mA | @ 3.3VDC supply; 50 Kbps; CL = 0 pF | 7 | |
| Total Supply Current vs Data Throughput (π161Uxx, 150 Kbps, side 2) | IDD2 | 2.35 | 3.53 | mA | @ 3.3VDC supply; 150 Kbps; CL = 0 pF | 7 | |
| Minimum External Air Gap (Clearance) | L (CLR) | 4 | mm | Measured from input terminals to output terminals, shortest distance through air | 7 | ||
| Minimum External Tracking (Creepage) | L (CRP) | 4 | mm | Measured from input terminals to output terminals, shortest distance path along body | 7 | ||
| Minimum Internal Gap (Internal Clearance) | 11 | µm | Insulation distance through insulation | 7 | |||
| Quiescent/Dynamic: Hysteresis, VDDx1 Undervoltage | VDDxUVH | 0.15 | V | 6 | |||
| IC Junction to Ambient Thermal Resistance (SOIC-16, π16xU3x) | θJA | 76 | °C/W | Thermocouple located at center of package underside | 7 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | pC | In accordance with DIN V VDE V 0884-10, eachπ160U3x/π161U3x/π162U3x /π163U3x is proof tested by applying an insulation test voltage ≥ 1326 V peak for 1 sec (partial discharge detection limit = 5 pC); | 8 |
CAD (KiCad official)
- Symbol:
π161U31 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOIC-16 (KiCad packages3D, STEP)
- 3D model files:
161u31-etched.step/161u31-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);161u31.step/161u31.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: 2Pai Semi datasheet (16 pp, sha256
d12e9cd6aa221f61, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).