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CD4049BM

Public Made by Adom

by adom

lingxingic Inverters, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD4049BM

lingxingic · Inverters · SOP-16

CD4049BM from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Positive supply voltage; the recommended VDD range is 3V to 15V referenced to VSS, and the absolute maximum supply voltage is 18V.
2 1Y output Data output of inverting buffer 1, which the datasheet describes as having high current output capability suitable for driving TTL or high capacitive loads.
3 1A input Data input of inverting buffer 1; the recommended input voltage is 0V to 15V, and inputs may exceed the supply voltage.
4 2Y output Data output of inverting buffer 2, which the datasheet describes as having high current output capability suitable for driving TTL or high capacitive loads.
5 2A input Data input of inverting buffer 2; the recommended input voltage is 0V to 15V, and inputs may exceed the supply voltage.
6 3Y output Data output of inverting buffer 3, which the datasheet describes as having high current output capability suitable for driving TTL or high capacitive loads.
7 3A input Data input of inverting buffer 3; the recommended input voltage is 0V to 15V, and inputs may exceed the supply voltage.
8 VSS power_in Ground supply voltage; the reference for all voltages in the datasheet (0V).
9 4A input Data input of inverting buffer 4; the recommended input voltage is 0V to 15V, and inputs may exceed the supply voltage.
10 4Y output Data output of inverting buffer 4, which the datasheet describes as having high current output capability suitable for driving TTL or high capacitive loads.
11 5A input Data input of inverting buffer 5; the recommended input voltage is 0V to 15V, and inputs may exceed the supply voltage.
12 5Y output Data output of inverting buffer 5, which the datasheet describes as having high current output capability suitable for driving TTL or high capacitive loads.
13 n.c. unconnected Not connected; the datasheet lists this pin as not connected internally.
14 6A input Data input of inverting buffer 6; the recommended input voltage is 0V to 15V, and inputs may exceed the supply voltage.
15 6Y output Data output of inverting buffer 6, which the datasheet describes as having high current output capability suitable for driving TTL or high capacitive loads.
16 n.c. unconnected Not connected; the datasheet lists this pin as not connected internally.

Key specifications

Parameter Value
Manufacturer lingxingic
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VDD -0.5 18 V 6
DC input current IIK -10 mA VI<-0.5V 6
input voltage VI -0.5 18 V 6
output clamping current IOK -10 10 mA VO<-0.5V or VO>VDD+0.5V 6
input/output current II/O -10 10 mA 6
supply current IDD 50 mA 6
storage temperature Tstg -65 150 ℃ 6
soldering temperature TL 260 ℃ 10s, SOP/TSSOP 6
supply voltage VDD 3 15 V 7
input voltage VI 0 15 V 7
ambient temperature Tamb -40 125 ℃ in free air 7
supply current IDD 4 uA Tamb=25℃; VIN=0V; VDD=5V 7
supply current IDD 8 uA Tamb=25℃; VIN=0V; VDD=10V 7
supply current IDD 16 uA Tamb=25℃; VIN=0V; VDD=15V 7
LOW-level output current IOL 2.9 mA Tamb=25℃; VO=0.4V; VIN=0V; VDD=5V 7
LOW-level output current IOL 10 mA Tamb=25℃; VO=0.5V; VIN=0V; VDD=10V 7
LOW-level output current IOL 20 mA Tamb=25℃; VO=1.5V; VIN=0V; VDD=15V 7
HIGH-level output current IOH -0.44 mA Tamb=25℃; VO=4.6V; VIN=0V; VDD=5V 7
HIGH-level output current IOH -1.4 mA Tamb=25℃; VO=2.5V; VIN=0V; VDD=5V 7
HIGH-level output current IOH -1.1 mA Tamb=25℃; VO=9.5V; VIN=0V; VDD=10V 7
HIGH-level output current IOH -3 mA Tamb=25℃; VO=13.5V; VIN=0V; VDD=15V 7
LOW-level output voltage VOL 0.05 V Tamb=25℃; VIN=0V; VDD=5V 7
HIGH-level output voltage VOH 4.95 V Tamb=25℃; VIN=0V; VDD=5V 7
HIGH-level output voltage VOH 9.95 V Tamb=25℃; VIN=0V; VDD=10V 7
HIGH-level output voltage VOH 14.95 V Tamb=25℃; VIN=0V; VDD=15V 7
LOW-level input voltage VIL 1.5 V Tamb=25℃; VIN=0V; VDD=5V 7
LOW-level input voltage VIL 3 V Tamb=25℃; VIN=0V; VDD=10V 7
LOW-level input voltage VIL 4 V Tamb=25℃; VIN=0V; VDD=15V 7
HIGH-level input voltage VIH 3.5 V Tamb=25℃; VIN=0V; VDD=5V 7
HIGH-level input voltage VIH 7 V Tamb=25℃; VIN=0V; VDD=10V 7
HIGH-level input voltage VIH 11 V Tamb=25℃; VIN=0V; VDD=15V 7
input leakage current II -1 1 uA Tamb=25℃; VIN=0,15V; VDD=15V 7
supply current IDD 30 uA Tamb=125℃; VIN=0V; VDD=5V 8
supply current IDD 60 uA Tamb=125℃; VIN=0V; VDD=10V 8
supply current IDD 120 uA Tamb=125℃; VIN=0V; VDD=15V 8
LOW-level output current IOL 2.3 mA Tamb=125℃; VO=0.4V; VIN=0V; VDD=5V 8
LOW-level output current IOL 8 mA Tamb=125℃; VO=0.5V; VIN=0V; VDD=10V 8
LOW-level output current IOL 16 mA Tamb=125℃; VO=1.5V; VIN=0V; VDD=15V 8
LOW-level output current IOL 3.5 mA Tamb=-40℃; VO=0.4V; VIN=0V; VDD=5V 8
LOW-level output current IOL 12 mA Tamb=-40℃; VO=0.5V; VIN=0V; VDD=10V 8
LOW-level output current IOL 24 mA Tamb=-40℃; VO=1.5V; VIN=0V; VDD=15V 8
HIGH-level output current IOH -0.36 mA Tamb=125℃; VO=4.6V; VIN=0V; VDD=5V 8
HIGH-level output current IOH -1.1 mA Tamb=125℃; VO=2.5V; VIN=0V; VDD=5V 8
HIGH-level output current IOH -0.9 mA Tamb=125℃; VO=9.5V; VIN=0V; VDD=10V 8
HIGH-level output current IOH -2.4 mA Tamb=125℃; VO=13.5V; VIN=0V; VDD=15V 8
HIGH to LOW propagation delay tPHL 35 70 ns nA to nY; VDD=5V; CL=50pF 8
HIGH to LOW propagation delay tPHL 15 30 ns nA to nY; VDD=10V; CL=50pF 8
HIGH to LOW propagation delay tPHL 12 25 ns nA to nY; VDD=15V; CL=50pF 8
LOW to HIGH propagation delay tPLH 50 100 ns nA to nY; VDD=5V; CL=50pF 8
LOW to HIGH propagation delay tPLH 25 50 ns nA to nY; VDD=10V; CL=50pF 8
LOW to HIGH propagation delay tPLH 20 40 ns nA to nY; VDD=15V; CL=50pF 8
HIGH to LOW output transition time tTHL 20 40 ns see Figure 6; VDD=5V; CL=50pF 8
HIGH to LOW output transition time tTHL 10 20 ns see Figure 6; VDD=10V; CL=50pF 8
HIGH to LOW output transition time tTHL 7 14 ns see Figure 6; VDD=15V; CL=50pF 8
LOW to HIGH output transition time tTLH 60 120 ns see Figure 6; VDD=5V; CL=50pF 8
LOW to HIGH output transition time tTLH 30 60 ns see Figure 6; VDD=10V; CL=50pF 8
LOW to HIGH output transition time tTLH 20 40 ns see Figure 6; VDD=15V; CL=50pF 8

CAD (KiCad official)

  • Symbol: CD4049BM
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4049bm-etched.step / cd4049bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4049bm.step / cd4049bm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (13 pp, sha256 fc5a1221af10c57e, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF