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Contents

README

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UC2875DWPTR

Texas Instruments · AC-DC Controllers And Regulators · SOIC-28-300mil

UC2875DWPTR from Texas Instruments, in a SOIC-28-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREF power_out Accurate 5V reference output delivering about 60mA, short-circuit limited, disabled in UVLO, bypass with a 0.1µF low-ESR capacitor to GND.
2 E/AOUT output Error amplifier output and gain stage for overall feedback control; levels below 1V force 0° phase shift.
3 EA- input Error amplifier inverting input, normally connected to the divider sensing the power supply output voltage.
4 EA+ input Error amplifier non-inverting input, normally connected to a reference voltage for comparison with the sensed output level.
5 CS+ input Non-inverting input of the current-fault comparator with internal 2.5V reference; exceeding 2.5V latches outputs off and starts a soft-start cycle.
6 SOFTSTART output Soft-start pin held at GND while VIN is below UVLO, then pulled up to about 4.8V by an internal 9µA source.
7 GND power_in Signal ground, reference for all voltages.
8 GND power_in Signal ground, reference for all voltages.
9 GND power_in Signal ground, reference for all voltages.
10 DELAYSET C-D input Programmed current from this pin to GND sets the turn-on delay for the C-D output pair.
11 N/C unconnected No connection.
12 OUTD output 2A totem-pole output D, part of the C-D pair driving the second half-bridge phase-shifted from A-B.
13 OUTC output 2A totem-pole output C, part of the C-D pair driving the second half-bridge phase-shifted from A-B.
14 VC power_in Supply for the output drivers; connect to a stable source above 3V (above 12V for best performance), bypassed to PWRGND.
15 VIN power_in Primary chip supply for logic and analog circuitry; connect to a stable source above 12V, inactive until VIN exceeds the UVLO threshold, bypass to GND.
16 PWRGND power_in Power ground for the output drivers; bypass VC to it with a ceramic capacitor, may be joined to signal ground at a single point.
17 OUTB output 2A totem-pole output B, part of the A-B pair driving one half-bridge synchronized with the clock.
18 OUTA output 2A totem-pole output A, part of the A-B pair driving one half-bridge synchronized with the clock.
19 N/C unconnected No connection.
20 GND power_in Signal ground, reference for all voltages.
21 GND power_in Signal ground, reference for all voltages.
22 GND power_in Signal ground, reference for all voltages.
23 DELAYSET A-B input Programmed current from this pin to GND sets the turn-on delay for the A-B output pair.
24 FREQSET passive A resistor and capacitor from this pin to GND set the oscillator frequency.
25 CLOCKSYNC bidirectional Outputs a clock signal or accepts a synchronization input higher in frequency than the local oscillator.
26 SLOPE passive A resistor from this pin to VCC sets the current used to generate the ramp, giving slope compensation or voltage feed-forward.
27 RAMP input Input to the PWM comparator; connect a capacitor to GND, with 1.3V offset between ramp input and PWM comparator.
28 GND power_in Signal ground, reference for all voltages.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-28-300mil
Category Power Management (PMIC)
Pins 28

CAD (KiCad official)

  • Symbol: UC2875DWPTR
  • Footprint: Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm
  • 3D model: SOIC-28-300mil (KiCad packages3D, STEP)
  • 3D model files: uc2875dwptr-etched.step / uc2875dwptr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); uc2875dwptr.step / uc2875dwptr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 4544bfc895c90421, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF