component
TPS65263RHBT
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS65263RHBT
Texas Instruments · DC-DC Converters · VQFN-32-EP(5x5)
TPS65263RHBT from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN3 | input | Enable for buck3; float to enable, and a resistor divider on this pin can set the buck3 input UVLO. |
| 2 | SDA | bidirectional | I2C interface data pin; absolute maximum is 7 V and recommended operating range is -0.1 V to 6.3 V. |
| 3 | SCL | input | I2C interface clock pin; absolute maximum is 7 V and recommended operating range is -0.1 V to 6.3 V. |
| 4 | AGND | power_in | Analog ground shared by the buck controllers and analog circuits, routed separately from high-current power grounds to the (-) terminal of the VIN bypass capacitor. |
| 5 | VOUT2 | input | Buck2 output voltage sense pin; absolute maximum is 7 V. |
| 6 | FB2 | input | Kelvin feedback sense pin for buck2 that connects to the buck2 resistor divider; recommended range is -0.1 V to 3 V. |
| 7 | COMP2 | passive | Buck2 error amplifier output and loop compensation pin, compensated with a series resistor and capacitor in peak current PWM mode. |
| 8 | SS2 | passive | Buck2 soft-start and tracking input with an internal 5 µA pullup; soft-start time is set by a capacitor to ground. |
| 9 | BST2 | passive | Bootstrap supply for the buck2 high-side gate driver; a 47 nF capacitor (recommended) connects from BST2 to LX2. |
| 10 | LX2 | passive | Buck2 switching node to the inductor and bootstrap capacitor, swinging from a diode drop below ground up to the PVIN2 voltage. |
| 11 | PGND2 | power_in | Buck2 power ground, to be placed as close as practical to the (-) terminal of the PVIN2 input ceramic capacitor. |
| 12 | PVIN2 | power_in | Buck2 input power supply, placed close to the input ceramic capacitor (suggested 10 µF); recommended input range is 4.5 V to 18 V. |
| 13 | PVIN3 | power_in | Buck3 input power supply, placed close to the input ceramic capacitor (suggested 10 µF); recommended input range is 4.5 V to 18 V. |
| 14 | PGND3 | power_in | Buck3 power ground, to be placed as close as practical to the (-) terminal of the PVIN3 input ceramic capacitor. |
| 15 | LX3 | passive | Buck3 switching node to the inductor and bootstrap capacitor, swinging from a diode drop below ground up to the PVIN3 voltage. |
| 16 | BST3 | passive | Bootstrap supply for the buck3 high-side gate driver; a 47 nF capacitor (recommended) connects from BST3 to LX3. |
| 17 | SS3 | passive | Buck3 soft-start and tracking input with an internal 5 µA pullup; soft-start time is set by a capacitor to ground. |
| 18 | COMP3 | passive | Buck3 error amplifier output and loop compensation pin, compensated with a series resistor and capacitor in peak current PWM mode. |
| 19 | FB3 | input | Kelvin feedback sense pin for buck3 that connects to the buck3 resistor divider; recommended range is -0.1 V to 3 V. |
| 20 | VOUT3 | input | Buck3 output voltage sense pin; absolute maximum is 7 V. |
| 21 | VOUT1 | input | Buck1 output voltage sense pin; absolute maximum is 7 V. |
| 22 | FB1 | input | Kelvin feedback sense pin for buck1 that connects to the buck1 resistor divider; recommended range is -0.1 V to 3 V. |
| 23 | COMP1 | passive | Buck1 error amplifier output and loop compensation pin, compensated with a series resistor and capacitor in peak current PWM mode. |
| 24 | SS1 | passive | Buck1 soft-start and tracking input with an internal 5 µA pullup; soft-start time is set by a capacitor to ground. |
| 25 | BST1 | passive | Bootstrap supply for the buck1 high-side gate driver; a 47 nF capacitor (recommended) connects from BST1 to LX1. |
| 26 | LX1 | passive | Buck1 switching node to the inductor and bootstrap capacitor, swinging from a diode drop below ground up to the PVIN1 voltage. |
| 27 | PGND1 | power_in | Buck1 power ground, to be placed as close as practical to the (-) terminal of the PVIN1 input ceramic capacitor. |
| 28 | PVIN1 | power_in | Buck1 input power supply, placed close to the input ceramic capacitor (suggested 10 µF); recommended input range is 4.5 V to 18 V. |
| 29 | VIN | power_in | Buck controller power supply; recommended input range is 4.5 V to 18 V. |
| 30 | V7V | power_out | Internal LDO output for the gate driver and internal controller; connect a 10 µF capacitor from this pin to power ground. |
| 31 | EN1 | input | Enable for buck1; float to enable, and a resistor divider on this pin can adjust the buck1 input UVLO. |
| 32 | EN2 | input | Enable for buck2; float to enable, and a resistor divider on this pin can adjust the buck2 input UVLO. |
| 33 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage PVIN1, PVIN2, PVIN3, VIN | PVIN1, PVIN2, PVIN3, VIN | -0.3 | 20 | V | 6 | ||
| Voltage LX1, LX2, LX3 | LX1, LX2, LX3 | -1 | 20 | V | maximum withstand voltage transient <20 ns | 6 | |
| Voltage BST1, BST2, BST3 | BST1, BST2, BST3 | -0.3 | 7 | V | referenced to LX1, LX2, LX3 pins respectively | 6 | |
| Voltage EN1, EN2, EN3, V7V, VOUT1, VOUT2, VOUT3, SCL, SDA | EN1, EN2, EN3, V7V, VOUT1, VOUT2, VOUT3, SCL, SDA | -0.3 | 7 | V | 6 | ||
| Voltage FB1, FB2, FB3, COMP1, COMP2, COMP3, SS1, SS2, SS3 | FB1, FB2, FB3, COMP1, COMP2, COMP3, SS1, SS2, SS3 | -0.3 | 3.6 | V | 6 | ||
| Voltage AGND, PGND1, PGND2, PGND3 | AGND, PGND1, PGND2, PGND3 | -0.3 | 0.3 | V | 6 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 6 | ||
| Storage temperature range | Tstg | -55 | 150 | °C | 6 | ||
| Input voltage range PVIN1, PVIN2, PVIN3, VIN | PVIN1, PVIN2, PVIN3, VIN | 4.5 | 18 | V | 6 | ||
| Voltage LX1, LX2, LX3 | LX1, LX2, LX3 | -0.8 | 18 | V | Maximum withstand voltage transient <20 ns | 6 | |
| Voltage BST1, BST2, BST3 | BST1, BST2, BST3 | -0.1 | 6.8 | V | referenced to LX1, LX2, LX3 pins respectively | 6 | |
| Voltage EN1, EN2, EN3, V7V, VOUT1, VOUT2, VOUT3, SCL, SDA | EN1, EN2, EN3, V7V, VOUT1, VOUT2, VOUT3, SCL, SDA | -0.1 | 6.3 | V | 6 | ||
| Voltage FB1, FB2, FB3, COMP1, COMP2, COMP3, SS1, SS2, SS3 | FB1, FB2, FB3, COMP1, COMP2, COMP3, SS1, SS2, SS3 | -0.1 | 3 | V | 6 | ||
| Operating ambient temperature | TA | -40 | 85 | °C | 6 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 6 | ||
| Junction-to-ambient thermal resistance | RθJA | 33.3 | °C/W | RHB (32 pins) package | 6 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 25.7 | °C/W | RHB (32 pins) package | 6 | ||
| Junction-to-board thermal resistance | RθJB | 7.4 | °C/W | RHB (32 pins) package | 6 | ||
| Junction-to-top characterization parameter | ψJT | 0.3 | °C/W | RHB (32 pins) package | 6 | ||
| Junction-to-board characterization parameter | ψJB | 7.3 | °C/W | RHB (32 pins) package | 6 | ||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 2.1 | °C/W | RHB (32 pins) package | 6 | ||
| V7V LDO output voltage | V7V | 6 | 6.3 | 6.6 | V | V7V load current = 0 A | 7 |
| VIN undervoltage lockout, rising | UVLO | 4 | 4.25 | 4.5 | V | VIN rising | 7 |
| VIN undervoltage lockout, falling | UVLO | 3.5 | 3.75 | 4 | V | VIN falling | 7 |
| Feedback voltage | VFB | 0.595 | 0.6 | 0.605 | V | VCOMP = 1.2 V, TJ = 25°C | 7 |
| Feedback voltage | VFB | 0.594 | 0.6 | 0.606 | V | VCOMP = 1.2 V, TJ = –40°C to 125°C | 7 |
| Soft start charging current | ISSX | 4.3 | 5 | 6 | µA | 7 | |
| Buck1 peak inductor current limit | ILIMIT1 | 4.5 | 5.5 | 6.5 | A | 7 | |
| Buck2/3 peak inductor current limit | ILIMIT2/3 | 2.6 | 3.3 | 4 | A | 7 | |
| Switching frequency | FSW | 550 | 600 | 650 | kHz | 7 | |
| Input high voltage SDA, SCL | II | -10 | 10 | µA | Input current SDA, SCL, VI = 0.4 to 4.5 V | 8 | |
| Maximum SCL clock frequency | ƒ(SCL) | 400 | kHz | 8 | |||
| Rise time of SCL signal | tRCL | 300 | ns | Capacitance of one bus line (pF) 20 + 0.1CB; not production tested | 8 | ||
| Rise time of SCL signal after a repeated START condition and after an acknowledge BIT | tRCL1 | 300 | ns | Capacitance of one bus line (pF) 20 + 0.1CB; not production tested | 8 | ||
| Fall time of SCL signal | tFCL | 300 | ns | Capacitance of one bus line (pF) 20 + 0.1CB; not production tested | 8 | ||
| Rise time of SDA signal | tRDA | 300 | ns | Capacitance of one bus line (pF) 20 + 0.1CB; not production tested | 8 | ||
| Fall time of SDA signal | tFDA | 300 | ns | Capacitance of one bus line (pF) 20 + 0.1CB; not production tested | 8 |
CAD (KiCad official)
- Symbol:
TPS65263RHBT - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
tps65263rhbt-etched.step/tps65263rhbt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps65263rhbt.step/tps65263rhbt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (48 pp, sha256
68fb2fd65d5ab84d, retrieved 2026-10-10, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).