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LT1761IS5-BYP#TRPBF
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Analog Devices Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, TSOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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Datasheet
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README
markdownLT1761IS5-BYP#TRPBF
Analog Devices · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · TSOT-23-5
LT1761IS5-BYP#TRPBF from Analog Devices, in a TSOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IN | power_in | Input supply pin, 1.8V to 20V operating range, withstands reverse voltage (±20V max), with a 1μF to 10μF bypass capacitor advised if far from the main input filter capacitor. |
| 2 | GND | power_in | Ground. |
| 3 | BYP | passive | Bypass pin, clamped internally to ±0.6V from ground, for a capacitor (max 0.01μF) from OUT to lower noise to a typical 20μVRMS, and left unconnected if not used. |
| 4 | ADJ | input | Error amplifier input of the adjustable device, regulated to 1.22V referenced to ground, internally clamped to ±7V, with 30nA bias current flowing into the pin, setting an output range of 1.22V to 20V. |
| 5 | OUT | power_out | Regulated output supplying up to 100mA to the load, requiring a minimum output capacitor of 1μF to prevent oscillations. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating Junction Temperature Range (E, I Grade) | TJ | -40 | 125 | °C | E, I Grade (Note 2) | 2 | |
| IN Pin Voltage | -20 | 20 | V | 2 | |||
| OUT Pin Voltage | -20 | 20 | V | 2 | |||
| Input to Output Differential Voltage | -20 | 20 | V | 2 | |||
| ADJ Pin Voltage | -7 | 7 | V | 2 | |||
| BYP Pin Voltage | -0.6 | 0.6 | V | 2 | |||
| SHDN Pin Voltage | -20 | 20 | V | 2 | |||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Lead Temperature (Soldering) | 300 | °C | 10 sec | 2 | |||
| Maximum Junction Temperature (TJMAX) | TJMAX | 150 | °C | Pin configuration header | 2 | ||
| Junction-to-Ambient Thermal Resistance | θJA | 250 | °C/W | Pin configuration header | 2 | ||
| Junction-to-Ambient Thermal Resistance (measured) | θJA | 125 | °C/W | Copper area topside 2500mm2, backside 2500mm2; board area 2500mm2 | 17 | ||
| Junction-to-Ambient Thermal Resistance (measured) | θJA | 130 | °C/W | Copper area topside 225mm2, backside 2500mm2; board area 2500mm2 | 17 | ||
| Junction-to-Ambient Thermal Resistance (measured) | θJA | 135 | °C/W | Copper area topside 100mm2, backside 2500mm2; board area 2500mm2 | 17 | ||
| Junction-to-Ambient Thermal Resistance (measured) | θJA | 150 | °C/W | Copper area topside 50mm2, backside 2500mm2; board area 2500mm2 | 17 | ||
| Minimum Input Voltage | 1.8 | 2.3 | V | ILOAD = 100mA, l | 4 | ||
| ADJ Pin Voltage | 1.205 | 1.22 | 1.235 | V | VIN = 2V, ILOAD = 1mA | 4 | |
| ADJ Pin Voltage | 1.19 | 1.22 | 1.25 | V | 2.3V < VIN < 20V, 1mA < ILOAD < 50mA, l | 4 | |
| ADJ Pin Voltage | 1.17 | 1.22 | 1.26 | V | 2.3V < VIN < 20V, 1mA < ILOAD < 100mA, l | 4 | |
| Line Regulation | 1 | 10 | mV | LT1761 (Note 3), ΔVIN = 2V to 20V, ILOAD = 1mA, l | 4 | ||
| Dropout Voltage | 0.1 | 0.19 | V | VIN = VOUT(NOMINAL), ILOAD = 1mA, l (Notes 5, 6, 11) | 5 | ||
| Dropout Voltage | 0.17 | 0.29 | V | VIN = VOUT(NOMINAL), ILOAD = 10mA, l (Notes 5, 6, 11) | 5 | ||
| Dropout Voltage | 0.24 | 0.38 | V | VIN = VOUT(NOMINAL), ILOAD = 50mA, l (Notes 5, 6, 11) | 5 | ||
| Dropout Voltage | 0.3 | 0.45 | V | VIN = VOUT(NOMINAL), ILOAD = 100mA (Notes 5, 6, 11) | 5 | ||
| GND Pin Current | 20 | 45 | μA | VIN = VOUT(NOMINAL), ILOAD = 0mA (Notes 5, 7), l | 6 | ||
| GND Pin Current | 55 | 100 | μA | VIN = VOUT(NOMINAL), ILOAD = 1mA (Notes 5, 7), l | 6 | ||
| GND Pin Current | 230 | 400 | μA | VIN = VOUT(NOMINAL), ILOAD = 10mA (Notes 5, 7), l | 6 | ||
| GND Pin Current | 1 | 2 | mA | VIN = VOUT(NOMINAL), ILOAD = 50mA (Notes 5, 7), l | 6 | ||
| GND Pin Current | 2.2 | 4 | mA | VIN = VOUT(NOMINAL), ILOAD = 100mA (Notes 5, 7), l | 6 | ||
| ADJ Pin Bias Current | 30 | 100 | nA | Notes 3, 8 | 6 | ||
| Shutdown Threshold (Off to On) | 0.8 | 2 | V | VOUT = Off to On, l | 6 | ||
| Shutdown Threshold (On to Off) | 0.25 | 0.65 | V | VOUT = On to Off, l | 6 | ||
| SHDN Pin Current | 0 | 0.5 | μA | VSHDN = 0V (Note 9), l | 6 | ||
| SHDN Pin Current | 1 | 3 | μA | VSHDN = 20V (Note 9), l | 6 | ||
| Quiescent Current in Shutdown | 0.01 | 0.1 | μA | VIN = 6V, VSHDN = 0V | 6 | ||
| Ripple Rejection | 55 | 65 | dB | VIN, VOUT = 1.5V (Avg), VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz, ILOAD = 50mA (Note 3) | 6 | ||
| Current Limit | 110 | 200 | mA | VIN = VOUT(NOMINAL) + 1V or 2.3V (Note 12), ΔVOUT = -5%, l | 6 | ||
| Input Reverse Leakage Current | 1 | mA | VIN = -20V, VOUT = 0V, l | 6 | |||
| Reverse Output Current | 5 | 10 | μA | VOUT = 1.22V, VIN < 1.22V (Note 3) | 6 |
CAD (KiCad official)
- Symbol:
LT1761IS5-BYP#TRPBF - Footprint:
Package_TO_SOT_SMD:TSOT-23-5 - 3D model: TSOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
lt1761is5-byp-trpbf-etched.step/lt1761is5-byp-trpbf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lt1761is5-byp-trpbf.step/lt1761is5-byp-trpbf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (22 pp, sha256
5e4fc36c022415d2, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).