component
SP40N25DP8
Public Made by Adomby adom
Siliup MOSFETs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSP40N25DP8
Siliup · MOSFETs · SOP-8
SP40N25DP8 from Siliup, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S1 | passive | Source of MOSFET 1 (N-channel), per the circuit diagram. |
| 2 | G1 | input | Gate of MOSFET 1; gate-source voltage rated ±20 V, threshold 1.0 to 2.5 V. |
| 3 | S2 | passive | Source of MOSFET 2 (N-channel), per the circuit diagram. |
| 4 | G2 | input | Gate of MOSFET 2; gate-source voltage rated ±20 V, threshold 1.0 to 2.5 V. |
| 5 | D2 | passive | Drain of MOSFET 2; drain-source voltage 40 V max, continuous drain current 6.3 A. |
| 6 | D2 | passive | Drain of MOSFET 2, internally common with pin 5; 40 V max drain-source voltage. |
| 7 | D1 | passive | Drain of MOSFET 1; drain-source voltage 40 V max, continuous drain current 6.3 A. |
| 8 | D1 | passive | Drain of MOSFET 1, internally common with pin 7; 40 V max drain-source voltage. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Siliup |
| Package | SOP-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Voltage | VDS | 40 | V | 2 | |||
| Gate-Source Voltage | VGS | -20 | 20 | V | 2 | ||
| Continuous Drain Current | ID | 6.3 | A | 2 | |||
| Pulsed Drain Current | IDM | 25.2 | A | 2 | |||
| Single Pulse Avalanche Energy | EAS | 51 | mJ | VDD=25V, VGS=10V, L=0.1mH, RG=25Ω (Note 1) | 2 | ||
| Power Dissipation | PD | 1.25 | W | 2 | |||
| Storage Temperature Range | TSTG | -55 | 150 | ℃ | 2 | ||
| Operating Junction Temperature Range | TJ | -55 | 150 | ℃ | 2 | ||
| Thermal Resistance Junction-to-Ambient | RθJA | 100 | ℃/W | 2 | |||
| Drain-Source Breakdown Voltage | BVDSS | 40 | V | VGS=0V, ID=250uA | 2 | ||
| Drain-Source Leakage Current | IDSS | 1 | uA | VDS=32V, VGS=0V | 2 | ||
| Gate-Source Leakage Current | IGSS | -100 | 100 | nA | VGS=±20V, VDS=0V | 2 | |
| Gate Threshold Voltage | VGS(th) | 1 | 1.5 | 2.5 | V | VGS=VDS, ID=250uA | 2 |
| Static Drain-Source On-Resistance (VGS=10V) | RDS(ON) | 25 | 32 | mΩ | VGS=10V, ID=6A | 2 | |
| Static Drain-Source On-Resistance (VGS=4.5V) | RDS(ON) | 35 | 45 | mΩ | VGS=4.5V, ID=4A | 2 | |
| Diode Forward Voltage | VSD | 1.2 | V | VGS=0V, IS=1A | 2 | ||
| Maximum Body-Diode Continuous Current | IS | 6.3 | A | 2 |
CAD (KiCad official)
- Symbol:
SP40N25DP8 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
sp40n25dp8-etched.step/sp40n25dp8-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sp40n25dp8.step/sp40n25dp8.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Siliup datasheet (5 pp, sha256
60b297bbb38413f1, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).