542MLFT from RENESAS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	ICLK	input	Clock input; input frequency up to 156 MHz, with VIH of VDD/2+1 and VIL of VDD/2-1 per the DC characteristics.
2	VDD	power_in	Power supply, connect to +3.3 V or +5 V (3.0 V to 5.5 V operating) with a 0.01 µF decoupling capacitor to ground.
3	GND	power_in	Connect to ground.
4	S0	input	Select 0 for output clock, connect to GND or VDD per the decoding table, with internal pull-up resistor.
5	S1	input	Select 1 for output clock, connect to GND or VDD per the decoding table, with internal pull-up resistor.
6	OE	input	Output Enable that tri-states both output clocks when low, with internal pull-up resistor.
7	CLK/2	output	Clock output per the decoding table, a low-skew divide by two of the pin 8 clock.
8	CLK	output	Clock output per the decoding table, with nominal output impedance of 20 Ω.

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	SOIC-8
Category	Clock and Timing
Pins	8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Operating Voltage	VDD	3		5.5	V		4
Input High Voltage	VIH	2			V	S0, S1, OE	4
Input Low Voltage	VIL			0.8	V	S0, S1, OE	4
Output High Voltage	VOH	2.4			V	IOH = -25 mA	4
Output Low Voltage	VOL			0.4	V	IOL = 25 mA	4
Operating Supply Current	IDD			11	mA	No Load, 5.0 V, 11 sel	4
Operating Supply Current	IDD			7	mA	No Load, 3.3 V, 11 sel	4
Short Circuit Current	IOS	-40		40	mA		4
Input Capacitance	CIN		4		pF	S0, S1, OE	4
Nominal Output Impedance	ZO		20		Ω	at VDD/2	4
Input Frequency, clock input		0		156	MHz	VDD = 5 V	4
Output Rise Time	tOR			1	ns	0.8 to 2.0 V	4
Output Fall Time	tOF			1	ns	2.0 to 0.8 V	4
Duty Cycle		45		55	%	at VDD/2	4
Skew of Output Clocks				500	ps	rising edges at VDD/2	4
Propagation Delay				15	ns	ICLK to CLK	4
Supply Voltage (absolute maximum)	VDD			7	V		3
All Inputs and Outputs (absolute maximum)		-0.5			V	-0.5 V to VDD+0.5 V	3
Storage Temperature		-65		150	°C		3
Junction Temperature				125	°C		3
Soldering Temperature				260	°C		3
Ambient Operating Temperature (commercial)		0		70	°C		3
Power Supply Voltage		3		5.5	V	measured in respect to GND	3
Thermal Resistance Junction to Ambient	θJA			150	°C/W	Still air	4
Thermal Resistance Junction to Ambient	θJA			140	°C/W	1 m/s air flow	4
Thermal Resistance Junction to Ambient	θJA			120	°C/W	3 m/s air flow	4
Thermal Resistance Junction to Case	θJC			40	°C/W		4

CAD (KiCad official)

Symbol: 542MLFT
Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
3D model: SOIC-8 (KiCad packages3D, STEP)
3D model files: 542mlft-etched.step / 542mlft-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); 542mlft.step / 542mlft.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (7 pp, sha256 031c58d21a671ced, retrieved 2026-11-02, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

542MLFT

Verified 542MLFT

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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