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Contents

README

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SI522A

Nanjing Zhongke Microelectronics · RFID ICs · QFN-32-EP(5x5)

SI522A from Nanjing Zhongke Microelectronics, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SDI input I2C bus input (mode-dependent function, see Chapter 8 Digital interface).
2 PVDD power_in Pad power supply. 2.5 V to 3.6 V; VDD(PVDD) must be equal to or smaller than VDDD.
3 DVDD power_in Digital power supply. 2.5 V to 3.6 V; VDDA, VDDD, and VDD(TVDD) must be at the same voltage.
4 DVSS power_in Digital ground (0 V reference for the digital core).
5 PVSS power_in Pad power supply ground (0 V return for PVDD).
6 NRSTPD input Not Reset and Power-Down. When LOW, internal current sinks are switched off, oscillator is inhibited, and input pads are disconnected from the outside world. A rising edge starts the internal reset phase.
7 MFIN input Communication interface input; accepts a digital serial data stream (S2C / secondary interface).
8 MFOUT output Communication interface output; delivers a digital serial data stream (S2C / secondary interface).
9 SVDD power_in Provides power to the MFIN/MFOUT interface pads. 2.5 V to 3.6 V.
10 TVSS power_in Transmitter ground; supplies the output stage of TX1 and TX2 (0 V return for the RF driver).
11 TX1 output Transmitter 1: delivers the modulated 13.56 MHz energy carrier to drive the reader/writer antenna.
12 TVDD power_in Transmitter power supply for the TX1/TX2 output stage. 2.5 V to 3.6 V; continuous-wave supply current ~20 mA typ (30 mA max).
13 TX2 output Transmitter 2: delivers the modulated 13.56 MHz energy carrier to drive the reader/writer antenna (complementary/anti-phase driver).
14 TVSS power_in Transmitter ground; supplies the output stage of TX1 and TX2 (second TVSS pin for the RF driver return).
15 AVDD power_in Analog power supply. 2.5 V to 3.6 V; IDDA ~3 mA typ with receiver on, ~0.9 mA with receiver off.
16 VMID passive Internal reference voltage output; requires an external decoupling capacitor to AVSS.
17 RX input Receiver input; connects to the antenna receive path via an external RC network.
18 AVSS power_in Analog ground (0 V reference for AVDD and the analog front-end).
19 AUX1 output Auxiliary output; used for testing/analog test multiplexer output.
20 AUX2 output Auxiliary output; used for testing/analog test multiplexer output.
21 OSCIN input Crystal oscillator input: input to the inverting amplifier of the oscillator. Also the input for an externally generated clock (fosc = 27.12 MHz).
22 OSCOUT output Crystal oscillator output: output of the inverting amplifier of the 27.12 MHz oscillator.
23 IRQ output Interrupt request: output that signals an interrupt event to the host controller.
24 SDA/NSS/RX bidirectional Muxed host-interface pin. I2C: SDA serial data. SPI: NSS chip-select input. UART: RX (address input for the UART configuration).
25 D1/ADR_5 bidirectional Test port D1 in test mode, or I2C bus address bit 5 (ADR_5) in I2C mode.
26 D2/ADR_4 bidirectional Test port D2, or I2C bus address bit 4 (ADR_4) input.
27 D3/ADR_3 bidirectional Test port D3, or I2C bus address bit 3 (ADR_3) input.
28 D4/ADR_2 bidirectional Test port D4, or I2C bus address bit 2 (ADR_2) input.
29 D5/ADR_1/SCK/DTRQ bidirectional Muxed host-interface pin. Test: D5. I2C: ADR_1 address bit 1. SPI: SCK serial clock input. UART: DTRQ (UART data-request output to controller).
30 D6/ADR_0/MOSI/MX bidirectional Muxed host-interface pin. Test: D6. I2C: ADR_0 address bit 0. SPI: MOSI (Master Out Slave In). UART: MX (UART output to controller).
31 D7/SCL/MISO/TX bidirectional Muxed host-interface pin. Test: D7. I2C: SCL clock. SPI: MISO (Master In Slave Out). UART: TX (UART data output to controller).
32 EA input External address input; can be used to define/enable the I2C address selection (tie to VDD or GND per host-interface configuration).

Key specifications

Parameter Value
Manufacturer Nanjing Zhongke Microelectronics
Package QFN-32-EP(5x5)
Category RF And Wireless
Pins 32

CAD (KiCad official)

  • Symbol: SI522A
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Nanjing Zhongke Microelectronics datasheet (109 pp, sha256 dac9a4a2e0c08099, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF