component
HX24LC512BDRG
Public Made by Adomby adom
HANSCHIP semiconductor EEPROM, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownHX24LC512BDRG
HANSCHIP semiconductor · EEPROM · SOP-8
HX24LC512BDRG from HANSCHIP semiconductor, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Address input hardwired to GND or VCC to set the device address (up to eight devices on a bus); internally pulled down to GND if left floating. |
| 2 | A1 | input | Address input hardwired to GND or VCC to set the device address; internally pulled down to GND if left floating. |
| 3 | NC | unconnected | No connect. |
| 4 | GND | power_in | Ground. |
| 5 | SDA | bidirectional | Bidirectional serial data pin, open-drain driven and may be wire-ORed with other open-drain or open-collector devices, needing an external pull-up. |
| 6 | SCL | input | Serial clock input that clocks data into the EEPROM on the positive edge and out on the negative edge. |
| 7 | WP | input | Write protect input: GND allows normal writes, VCC inhibits all writes to memory; internally pulled down to GND if left floating. |
| 8 | VCC | power_in | Power supply, 1.8V to 5.5V operating range. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HANSCHIP semiconductor |
| Package | SOP-8 |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (absolute maximum) | VCC | 6.5 | V | 9 | |||
| Input / Output Voltage | VO | -0.3 | V | 9 | |||
| Operating Ambient Temperature (absolute maximum) | Tamb | -40 | 85 | °C | 9 | ||
| Storage Temperature | Tstg | -65 | 125 | °C | 9 | ||
| Lead Temperature (Soldering) | TL | 245 | °C | Soldering, 10 seconds | 9 | ||
| Supply Voltage (recommended operating range) | VCC | 1.7 | 5.5 | V | TA = -40 °C to +85 °C | 9 | |
| Operating Ambient Temperature (recommended operating range) | TA | -40 | 85 | °C | 9 | ||
| Supply Voltage VCC1 | VCC1 | 1.8 | 5.5 | V | 9 | ||
| Supply Voltage VCC2 | VCC2 | 2.5 | 5.5 | V | 9 | ||
| Supply Voltage VCC3 | VCC3 | 2.7 | 5.5 | V | 9 | ||
| Supply Voltage VCC4 | VCC4 | 4.5 | 5.5 | V | 9 | ||
| Supply Current READ | ICC1 | 0.4 | 1 | mA | VCC = 5.0V; READ at 400 kHz | 9 | |
| Supply Current WRITE | ICC2 | 2 | 3 | mA | VCC = 5.0V; WRITE at 400 kHz | 9 | |
| Standby Current | ISB1 | 0.6 | 1 | µA | VCC = 1.7V; VIN = VCC or VSS | 9 | |
| Standby Current | ISB2 | 1 | 2 | µA | VCC = 2.5V; VIN = VCC or VSS | 9 | |
| Standby Current | ISB4 | 1 | 5 | µA | VCC = 5.0V; VIN = VCC or VSS | 9 | |
| Input Leakage Current | ILI | 0.1 | 3 | µA | VIN = VCC or VSS | 9 | |
| Output Leakage Current | ILO | 0.05 | 3 | µA | VOUT = VCC or VSS | 9 | |
| Input Low Level | VIL | -0.3 | V | 9 | |||
| Output Low Level | VOL3 | 0.4 | V | VCC = 5.0V; IOL = 3.0 mA | 9 | ||
| Output Low Level | VOL1 | 0.2 | V | VCC = 1.7V; IOL = 0.15 mA | 9 | ||
| Input/Output Capacitance (SDA) | CI/O | 8 | pF | VI/O = 0V | 10 | ||
| Input Capacitance (A0, A1, A2, SCL) | CIN | 6 | pF | VIN = 0V | 10 | ||
| Clock Frequency, SCL | fSCL | 400 | kHz | 1.7-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Clock Frequency, SCL | fSCL | 1000 | kHz | 5.0-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Clock Pulse Width Low | tLOW | 1.2 | µs | 1.7-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Clock Pulse Width Low | tLOW | 0.6 | µs | 5.0-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Clock Pulse Width High | tHIGH | 0.6 | µs | 1.7-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Clock Pulse Width High | tHIGH | 0.4 | µs | 5.0-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Noise Suppression Time | tI | 50 | ns | 1.7-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Clock Low to Data Out Valid | tAA | 0.1 | 0.9 | µs | 1.7-volt column; CL = 1 TTL Gate and 100 pF | 10 | |
| Clock Low to Data Out Valid | tAA | 0.09 | 0.9 | µs | 5.0-volt column; CL = 1 TTL Gate and 100 pF | 10 | |
| Bus free time before new transmission | tBUF | 1.2 | µs | 1.7-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Bus free time before new transmission | tBUF | 0.5 | µs | 5.0-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Start Hold Time | tHD.STA | 0.6 | µs | 1.7-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Start Hold Time | tHD.STA | 0.25 | µs | 5.0-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Start Setup Time | tSU.STA | 0.6 | µs | 1.7-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Start Setup Time | tSU.STA | 0.25 | µs | 5.0-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Data In Hold Time | tHD.DAT | 0 | µs | 1.7-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Inputs Rise Time | tR | 0.3 | µs | 1.7-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Inputs Fall Time | tF | 300 | ns | 1.7-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Stop Setup Time | tSU.STO | 0.6 | µs | 1.7-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Stop Setup Time | tSU.STO | 0.25 | µs | 5.0-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Data Out Hold Time | tDH | 50 | ns | 1.7-volt column; CL = 1 TTL Gate and 100 pF | 10 | ||
| Write Cycle Time | tWR | 5 | 5 | ms | 1.7-volt column | 10 | |
| Write Cycle Time | tWR | 5 | ms | 5.0-volt column | 10 |
CAD (KiCad official)
- Symbol:
HX24LC512BDRG - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
hx24lc512bdrg-etched.step/hx24lc512bdrg-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);hx24lc512bdrg.step/hx24lc512bdrg.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HANSCHIP semiconductor datasheet (15 pp, sha256
aa5120fd8a23d970, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).