component

OP07CDR

Public Made by Adom

by adom

Texas Instruments Precision OpAmps, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

componentop-amp-cmpop07cdr
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Contents

README

markdown

OP07CDR

Texas Instruments · Precision OpAmps · SOIC-8

OP07CDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OFFSET N1 input Offset null pin 1. Connect one end of an external 20 kΩ potentiometer here; the wiper goes to VCC+ to trim the input offset voltage.
2 IN- input Inverting input of the op-amp. Common-mode input voltage range ±13 V typ at VCC±=±15 V; input bias current ±1.8 nA typ.
3 IN+ input Non-inverting input of the op-amp. Common-mode input voltage range ±13 V typ at VCC±=±15 V; input bias current ±1.8 nA typ.
4 VCC- power_in Negative supply rail. Operating range -3 V to -18 V (referenced to VCC+ midpoint); absolute maximum -22 V.
5 NC unconnected No internal connection. Leave floating or tie to any convenient net.
6 OUT output Op-amp output. Peak output voltage ±13 V typ into RL ≥ 10 kΩ; output may be shorted to ground or either supply indefinitely.
7 VCC+ power_in Positive supply rail. Operating range +3 V to +18 V; absolute maximum +22 V. Also serves as the reference for the offset-null potentiometer wiper.
8 OFFSET N2 input Offset null pin 2. Connect the other end of the external 20 kΩ potentiometer here; potentiometer wiper returns to VCC+ for offset-voltage trimming. Adjustment range ±4 mV.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Op-amp/Cmp
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • OP07CDRD
  • OP07CDR
  • OP07CDRP

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC+ VCC+ 22 V 3
Supply voltage VCC– VCC– -22 V 3
Differential input voltage -30 30 V 3
Input voltage range (either input) VI -22 22 V 3
Package thermal impedance, junction to free air (D package) θJA 97 °C/W D package 3
Operating virtual-junction temperature TJ 150 °C 3
Lead temperature 260 °C 1,6 mm (1/16 in) from case for 10 s 3
Storage temperature range Tstg -65 150 °C 3
Supply voltage VCC± VCC± 3 18 V 3
Common-mode input voltage VIC -13 13 V VCC± = ±15 V 3
Operating free-air temperature TA 0 70 °C 3
Input offset voltage VIO 60 150 µV VO = 0 V, RS = 50 Ω, TA = 25°C 4
Input offset voltage VIO 85 250 µV VO = 0 V, RS = 50 Ω, TA = 0°C to 70°C 4
Temperature coefficient of input offset voltage αVIO 0.5 2.5 µV/°C VO = 0 V, RS = 50 Ω, TA = 0°C to 70°C 4
Offset adjustment range -4 4 mV RS = 20 kΩ, See Figure 1, TA = 25°C 4
Input offset current IIO 0.8 6 nA TA = 25°C 4
Input offset current IIO 1.6 8 nA TA = 0°C to 70°C 4
Temperature coefficient of input offset current αIIO 12 50 pA/°C TA = 0°C to 70°C 4
Input bias current IIB -12 1.8 12 nA TA = 25°C 4
Input bias current IIB -14 2.2 14 nA TA = 0°C to 70°C 4
Temperature coefficient of input bias current αIIB 18 50 pA/°C TA = 0°C to 70°C 4
Common-mode input voltage range VICR -13 14 V TA = 25°C 4
Common-mode input voltage range VICR -13 13.5 V TA = 0°C to 70°C 4
Peak output voltage VOM -12 13 V RL ≥ 10 kΩ, TA = 25°C 4
Peak output voltage VOM -11.5 12.8 V RL ≥ 2 kΩ, TA = 25°C 4
Peak output voltage VOM -11 12.6 V RL ≥ 2 kΩ, TA = 0°C to 70°C 4
Large-signal differential voltage amplification AVD 100 400 V/mV VCC = 15 V, VO = 1.4 V to 11.4 V, RL ≥ 500 kΩ, TA = 25°C 4
Large-signal differential voltage amplification AVD 120 400 V/mV VO = ±10 V, RL = 2 kΩ, TA = 25°C 4
Unity-gain bandwidth B1 0.4 0.6 MHz TA = 25°C 4
Input resistance ri 8 33 MΩ TA = 25°C 4
Common-mode rejection ratio CMRR 100 120 dB VIC = ±13 V, RS = 50 Ω, TA = 25°C 4
Common-mode rejection ratio CMRR 97 120 dB VIC = ±13 V, RS = 50 Ω, TA = 0°C to 70°C 4
Supply-voltage sensitivity (ΔVIO/ΔVCC) kSVS 7 32 µV/V VCC+ = ±3 V to ±18 V, RS = 50 Ω, TA = 25°C 4
Supply-voltage sensitivity (ΔVIO/ΔVCC) kSVS 10 51 µV/V VCC+ = ±3 V to ±18 V, RS = 50 Ω, TA = 0°C to 70°C 4
Power dissipation PD 80 150 mW VO = 0, No load 4
Power dissipation PD 4 8 mW VCC+ = ±3 V, VO = 0, No load 4

CAD (KiCad official)

  • Symbol: OP07CDR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: op07cdr-etched.step / op07cdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); op07cdr.step / op07cdr.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
op07cdr.step 122 KB You want the bare part, or you mark your own boards.
op07cdr-etched.step 1.6 MB You want the part with OP07CDR already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 396 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (15 pp, sha256 c68e9ffdd5c60c1c, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF