component
SN74HC164PW
Public Made by Adomby adom
lingxingic Shift Registers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74HC164PW
lingxingic · Shift Registers · TSSOP-14
SN74HC164PW from lingxingic, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DSA | input | Gated serial data input DSA; either DSA or DSB can act as a high-level enable for the other serial input, and data is shifted in on the CP rising edge. |
| 2 | DSB | input | Gated serial data input DSB; either DSB or DSA can act as a high-level enable for the other serial input, and data is shifted in on the CP rising edge. |
| 3 | Q0 | output | Parallel data output Q0, which is forced low when MR is low and otherwise follows the shift register contents. |
| 4 | Q1 | output | Parallel data output Q1, which is forced low when MR is low and otherwise follows the shift register contents. |
| 5 | Q2 | output | Parallel data output Q2, which is forced low when MR is low and otherwise follows the shift register contents. |
| 6 | Q3 | output | Parallel data output Q3, which is forced low when MR is low and otherwise follows the shift register contents. |
| 7 | GND | power_in | Ground reference, 0 V. |
| 8 | CP | input | Clock input; the register shifts data on the rising edge of CP. |
| 9 | MR | input | Asynchronous master reset, active low; when low it clears the register and forces all outputs Q0 to Q7 low independent of the other inputs. |
| 10 | Q4 | output | Parallel data output Q4, which is forced low when MR is low and otherwise follows the shift register contents. |
| 11 | Q5 | output | Parallel data output Q5, which is forced low when MR is low and otherwise follows the shift register contents. |
| 12 | Q6 | output | Parallel data output Q6, which is forced low when MR is low and otherwise follows the shift register contents. |
| 13 | Q7 | output | Parallel data output Q7, which is forced low when MR is low and otherwise follows the shift register contents. |
| 14 | VCC | power_in | Supply voltage; recommended operating range 2.0 V to 6.0 V, with an absolute maximum of 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | lingxingic |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74HC164PW - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74hc164pw-etched.step/sn74hc164pw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74hc164pw.step/sn74hc164pw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: lingxingic datasheet (20 pp, sha256
fef1526317b718fd, retrieved 2026-10-09, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).