component
MIC5209-5.0YM-TR
Public Made by Adomby adom
Microchip Tech Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownMIC5209-5.0YM-TR
Microchip Tech · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8
MIC5209-5.0YM-TR from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN | input | CMOS-compatible enable input: logic-high (above 2.0 V) enables the regulator and logic-low (0.4 V max, 0.18 V for full shutdown) shuts it down; connect to IN if the enable function is not needed. |
| 2 | IN | power_in | Supply input, specified for +2.5 V to +16 V operation (absolute maximum ±20 V); a 1 µF capacitor from IN to GND is recommended if the input is a battery or has more than 10 inches of wire to the AC filter capacitor. |
| 3 | OUT | power_out | Regulator output that requires an output capacitor to GND to prevent oscillation: 1 µF minimum without the 470 pF bypass capacitor, or 2.2 µF minimum with it. |
| 4 | BYP | passive | Reference bypass for fixed-voltage devices: an optional 470 pF capacitor to GND reduces output noise, and the pin can be left open; for ADJ devices this pin is the ADJ feedback input instead. |
| 5 | GND | power_in | Ground return; pins 5 through 8 are internally connected to each other on the SOIC-8 package. |
| 6 | GND | power_in | Ground return; internally connected to pins 5, 7 and 8 on the SOIC-8 package. |
| 7 | GND | power_in | Ground return; internally connected to pins 5, 6 and 8 on the SOIC-8 package. |
| 8 | GND | power_in | Ground return; internally connected to pins 5 through 7 on the SOIC-8 package. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output Voltage Accuracy | VOUT | -1 | 1 | % | % variation from nominal VOUT; TJ = +25°C; VIN = VOUT + 1V; IL = 100 µA | 5 | |
| Output Voltage Accuracy | VOUT | -2 | 2 | % | % variation from nominal VOUT; bold values: -40°C ≤ TJ ≤ +125°C; VIN = VOUT + 1V; IL = 100 µA | 5 | |
| Line Regulation | ΔVOUT/VOUT | 0.009 | 0.05 | % | VIN = VOUT + 1V to 16V | 5 | |
| Line Regulation | ΔVOUT/VOUT | 0.1 | % | VIN = VOUT + 1V to 16V; bold: -40°C ≤ TJ ≤ +125°C | 5 | ||
| Load Regulation | ΔVOUT/VOUT | 0.05 | 0.5 | % | IL = 100 µA to 500 mA, Note 3 | 5 | |
| Load Regulation | ΔVOUT/VOUT | 0.7 | % | IL = 100 µA to 500 mA, Note 3; bold: -40°C ≤ TJ ≤ +125°C | 5 | ||
| Dropout Voltage (Note 4) | VIN - VOUT | 10 | 60 | mV | IL = 100 µA | 5 | |
| Dropout Voltage (Note 4) | VIN - VOUT | 80 | mV | IL = 100 µA; bold: -40°C ≤ TJ ≤ +125°C | 5 | ||
| Dropout Voltage (Note 4) | VIN - VOUT | 115 | 175 | mV | IL = 50 mA | 5 | |
| Dropout Voltage (Note 4) | VIN - VOUT | 250 | mV | IL = 50 mA; bold: -40°C ≤ TJ ≤ +125°C | 5 | ||
| Dropout Voltage (Note 4) | VIN - VOUT | 165 | 300 | mV | IL = 150 mA | 5 | |
| Dropout Voltage (Note 4) | VIN - VOUT | 400 | mV | IL = 150 mA; bold: -40°C ≤ TJ ≤ +125°C | 5 | ||
| Dropout Voltage (Note 4) | VIN - VOUT | 350 | 500 | mV | IL = 500 mA | 5 | |
| Dropout Voltage (Note 4) | VIN - VOUT | 600 | mV | IL = 500 mA; bold: -40°C ≤ TJ ≤ +125°C | 5 | ||
| Ground Pin Current (Note 5, Note 6) | IGND | 80 | 130 | µA | VEN ≥ 3.0V, IOUT = 100 µA | 5 | |
| Ground Pin Current (Note 5, Note 6) | IGND | 170 | µA | VEN ≥ 3.0V, IOUT = 100 µA; bold: -40°C ≤ TJ ≤ +125°C | 5 | ||
| Ground Pin Current (Note 5, Note 6) | IGND | 350 | 650 | µA | VEN ≥ 3.0V, IOUT = 50 mA | 5 | |
| Ground Pin Current (Note 5, Note 6) | IGND | 900 | µA | VEN ≥ 3.0V, IOUT = 50 mA; bold: -40°C ≤ TJ ≤ +125°C | 5 | ||
| Ground Pin Current (Note 5, Note 6) | IGND | 1.8 | 2.5 | mA | VEN ≥ 3.0V, IOUT = 150 mA | 5 | |
| Ground Pin Current (Note 5, Note 6) | IGND | 3 | mA | VEN ≥ 3.0V, IOUT = 150 mA; bold: -40°C ≤ TJ ≤ +125°C | 5 | ||
| Ground Pin Current (Note 5, Note 6) | IGND | 8 | 20 | mA | VEN ≥ 3.0V, IOUT = 500 mA | 5 | |
| Ground Pin Current (Note 5, Note 6) | IGND | 25 | mA | VEN ≥ 3.0V, IOUT = 500 mA; bold: -40°C ≤ TJ ≤ +125°C | 5 | ||
| Ground Pin Quiescent Current (Note 6) | IGND | 0.05 | 3 | µA | VEN ≤ 0.4V (shutdown) | 5 | |
| Ground Pin Quiescent Current (Note 6) | IGND | 0.1 | 8 | µA | VEN ≤ 0.18V (shutdown) | 5 | |
| Current Limit | ILIMIT | 700 | 900 | mA | 5 | ||
| Current Limit | ILIMIT | 1000 | mA | VOUT = 0V; bold: -40°C ≤ TJ ≤ +125°C | 5 | ||
| Enable Input Logic-Low Voltage | VENL | 0.4 | V | VEN = Logic-low (Regulator shutdown) | 6 | ||
| Enable Input Logic-Low Voltage | VENL | 0.18 | V | VEN = Logic-low (Regulator shutdown); bold: -40°C ≤ TJ ≤ +125°C | 6 | ||
| Enable Input Logic-High Voltage | VENH | 2 | V | VEN = Logic-high (Regulator enabled) | 6 | ||
| Enable Input Current | IENL | 0.01 | -1 | µA | VENL ≤ 0.4V | 6 | |
| Enable Input Current | IENL | 0.01 | -2 | µA | VENL ≤ 0.18V | 6 | |
| Enable Input Current | IENH | 5 | 20 | µA | VENH ≥ 2.0V | 6 | |
| Enable Input Current | IENH | 25 | µA | VENH ≥ 2.0V; bold: -40°C ≤ TJ ≤ +125°C | 6 | ||
| Enable Input Current | IENH | 30 | µA | VENH ≥ 16V | 6 | ||
| Enable Input Current | IENH | 50 | µA | VENH ≥ 16V; bold: -40°C ≤ TJ ≤ +125°C | 6 | ||
| Supply Voltage (VIN) | VIN | -20 | 20 | V | 4 | ||
| ESD Rating (DFN, SOIC-8) HBM | 5 | kV | HBM | 4 | |||
| ESD Rating (DFN, SOIC-8) MM | 100 | V | MM | 4 | |||
| Storage Temperature Range | TS | -65 | 150 | °C | 7 | ||
| Lead Temperature | 260 | °C | Soldering, 5 sec. | 7 | |||
| Supply Voltage (VIN) | VIN | 2.5 | 16 | V | 4 | ||
| Junction Temperature | TJ | -40 | 125 | °C | 2.5V ≤ VOUT ≤ 15V | 7 | |
| Thermal Resistance SOIC-8 junction-to-ambient | θJA | 50 | °C/W | See Thermal Considerations for more information | 7 | ||
| Thermal Resistance SOIC-8 junction-to-case | θJC | 25 | °C/W | 7 |
CAD (KiCad official)
- Symbol:
MIC5209-5.0YM-TR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
mic5209-5-0ym-tr-etched.step/mic5209-5-0ym-tr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);mic5209-5-0ym-tr.step/mic5209-5-0ym-tr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (30 pp, sha256
46148b9c0d4d1f14, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).