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Contents

README

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TPESD12VS5UD

TECH PUBLIC · ESD And Surge Protection (TVS/ESD) · SOT-23-6

TPESD12VS5UD from TECH PUBLIC, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I/O1 passive ESD-protected I/O line (uni-directional, 12V VRWM max, 60pF max to ground) with a steering diode to the common node.
2 GND power_in Common ground node of the array, tied directly to the center node in the schematic; I/O pins are specified relative to ground.
3 I/O2 passive ESD-protected I/O line (uni-directional, 12V VRWM max, 60pF max to ground) with a steering diode to the common node.
4 I/O3 passive ESD-protected I/O line (uni-directional, 12V VRWM max, 60pF max to ground) with a steering diode to the common node.
5 GND power_in Ground/common node connection of the array, shown joined to the center node through a diode symbol in the schematic.
6 I/O4 passive ESD-protected I/O line (uni-directional, 12V VRWM max, 60pF max to ground) with a steering diode to the common node.

Key specifications

Parameter Value
Manufacturer TECH PUBLIC
Package SOT-23-6
Category Circuit Protection
Pins 6

CAD (KiCad official)

  • Symbol: TPESD12VS5UD
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-23-6 (KiCad packages3D, STEP)
  • 3D model files: tpesd12vs5ud-etched.step / tpesd12vs5ud-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tpesd12vs5ud.step / tpesd12vs5ud.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TECH PUBLIC datasheet (4 pp, sha256 b07b48f74f9fbda1, retrieved 2026-10-21, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF