component
CD4011BM
Public Unreviewedby Ray
HGSEMI Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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README
markdownCD4011BM
HGSEMI · Gates · SOIC-14
CD4011BM from HGSEMI, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I1 | input | Gate 1 input A. CMOS logic input; VIL max 1.5 V @ VDD=5 V, VIH min 3.5 V @ VDD=5 V. Input leakage <=0.3 uA typ at VDD=15 V. |
| 2 | I2 | input | Gate 1 input B. CMOS logic input paired with I1; NANDed to produce O1. |
| 3 | O1 | output | Gate 1 buffered NAND output = NAND(I1, I2). VOH >= VDD-0.05 V, VOL <= 0.05 V at |
| 4 | O2 | output | Gate 2 buffered NAND output = NAND(I3, I4). Buffered CMOS output. |
| 5 | I3 | input | Gate 2 input A. CMOS logic input. |
| 6 | I4 | input | Gate 2 input B. CMOS logic input paired with I3. |
| 7 | VSS | power_in | Ground / negative supply reference (0 V). All input logic levels referenced to VSS. |
| 8 | I5 | input | Gate 3 input A. CMOS logic input. |
| 9 | I6 | input | Gate 3 input B. CMOS logic input paired with I5. |
| 10 | O3 | output | Gate 3 buffered NAND output = NAND(I5, I6). |
| 11 | O4 | output | Gate 4 buffered NAND output = NAND(I7, I8). |
| 12 | I7 | input | Gate 4 input A. CMOS logic input. |
| 13 | I8 | input | Gate 4 input B. CMOS logic input paired with I7. |
| 14 | VDD | power_in | Positive supply. Recommended VDD = 3 V to 15 V; absolute max -0.5 V to +18 V. Quiescent current IDD <= 7.5 uA at VDD=5 V (25 degC). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | HGSEMI |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
Ordering variants
Same part, different packaging or reel option.
CD4011BM/TRCD4011BMBECD4011BMBNCD4011BMT/TR
CAD (KiCad official)
- Symbol:
CD4011BM - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
3D model downloads
Two STEP files. Same geometry, different body top:
| File | Size | Use it when |
|---|---|---|
cd4011bm.step |
195 KB | You want the bare part, or you mark your own boards. |
cd4011bm-etched.step |
1.9 MB | You want the part with CD4011BM already on it. |
The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 501 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: HGSEMI datasheet (10 pp, sha256
5f5ccfab60c3ae62, retrieved 2026-08-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).