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ADS8361IDBQR
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Texas Instruments Analog To Digital Converters (ADCs), SSOP-24-150mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownADS8361IDBQR
Texas Instruments · Analog To Digital Converters (ADCs) · SSOP-24-150mil
ADS8361IDBQR from Texas Instruments, in a SSOP-24-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BGND | power_in | Digital I/O ground; connect directly to analog ground (pin 12). |
| 2 | CH B1+ | input | Noninverting analog input, channel B1; fully differential input with the signal limited to AGND - 0.3 V to AVDD + 0.3 V. |
| 3 | CH B1- | input | Inverting analog input, channel B1; forms a differential pair with CH B1+ and must stay within AGND - 0.3 V to AVDD + 0.3 V. |
| 4 | CH B0+ | input | Noninverting analog input, channel B0; fully differential input with the signal limited to AGND - 0.3 V to AVDD + 0.3 V. |
| 5 | CH B0- | input | Inverting analog input, channel B0; forms a differential pair with CH B0+ and must stay within AGND - 0.3 V to AVDD + 0.3 V. |
| 6 | CH A1+ | input | Noninverting analog input, channel A1; fully differential input with the signal limited to AGND - 0.3 V to AVDD + 0.3 V. |
| 7 | CH A1- | input | Inverting analog input, channel A1; forms a differential pair with CH A1+ and must stay within AGND - 0.3 V to AVDD + 0.3 V. |
| 8 | CH A0+ | input | Noninverting analog input, channel A0; fully differential input with the signal limited to AGND - 0.3 V to AVDD + 0.3 V. |
| 9 | CH A0- | input | Inverting analog input, channel A0; forms a differential pair with CH A0+ and must stay within AGND - 0.3 V to AVDD + 0.3 V. |
| 10 | REFIN | input | Reference input; recommended reference input voltage is 1.2 V to 2.6 V (2.5 V nominal). |
| 11 | REFOUT | output | 2.5 V internal reference output. |
| 12 | AGND | power_in | Analog ground; connect directly to digital ground (pin 1). |
| 13 | AVDD | power_in | Analog power supply, +5 VDC (4.75 V to 5.25 V); decouple to analog ground with a 0.1 µF ceramic capacitor and a 10 µF tantalum capacitor. |
| 14 | M1 | input | Selects between the serial outputs: when LOW both Serial Output A and B are used; when HIGH Serial Output A carries both Channel A and Channel B data and Serial Output B is tri-stated. |
| 15 | M0 | input | Selects two-channel (LOW, with A0) or four-channel sequential (HIGH) operation. |
| 16 | A0 | input | Channel address select used with M0 in two-channel mode: HIGH selects Channels A1 and B1, LOW selects Channels A0 and B0; ignored in four-channel mode. |
| 17 | CONVST | input | Convert start; a LOW-to-HIGH transition switches the device from sample to hold mode, independent of the external clock (CONVST HIGH for at least 15 ns). |
| 18 | RD | input | Synchronization pulse for the serial output. |
| 19 | CS | input | Chip select; when LOW the serial outputs are active, and when HIGH they are tri-stated. |
| 20 | CLOCK | input | CMOS-compatible external clock input; sets the sampling rate as fSAMPLE(max) = CLOCK/20 (CLOCK period 100 ns to 10,000 ns). |
| 21 | BUSY | output | Goes HIGH during a conversion and returns LOW after the third LSB has been transmitted on Serial A or Serial B. |
| 22 | SERIAL DATA B | output | Serial output data word of channel information plus 16 data bits; data is valid on the falling edge of DCLOCK for 20 edges after the rising edge of RD. |
| 23 | SERIAL DATA A | output | Serial output data word of channel information plus 16 data bits; data is valid on the falling edge of DCLOCK for 20 edges after the rising edge of RD, and carries both Channel A and Channel B data when M1 is HIGH. |
| 24 | BVDD | power_in | Digital I/O power supply, 2.7 V to 5.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SSOP-24-150mil |
| Category | ADC/DAC/Data Conversion |
| Pins | 24 |
CAD (KiCad official)
- Symbol:
ADS8361IDBQR - Footprint:
Package_SO:SSOP-24_5.3x8.2mm_P0.65mm - 3D model: SSOP-24-150mil (KiCad packages3D, STEP)
- 3D model files:
ads8361idbqr-etched.step/ads8361idbqr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads8361idbqr.step/ads8361idbqr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
4ac7245c5e383f31, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).