component
SN74LV240APWR
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownSN74LV240APWR
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-20
SN74LV240APWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Output enable input for first group of buffers; active low to enable outputs, high places outputs in high-impedance state |
| 2 | 1A1 | input | Input to first buffer of group 1; inverted output appears on 1Y1 when 1OE is low |
| 3 | 2Y4 | tri_state | Inverted output from second group bit 4; high-impedance state when 2OE is high |
| 4 | 1A2 | input | Input to second buffer of group 1; inverted output appears on 1Y2 when 1OE is low |
| 5 | 2Y3 | tri_state | Inverted output from second group bit 3; high-impedance state when 2OE is high |
| 6 | 1A3 | input | Input to third buffer of group 1; inverted output appears on 1Y3 when 1OE is low |
| 7 | 2Y2 | tri_state | Inverted output from second group bit 2; high-impedance state when 2OE is high |
| 8 | 1A4 | input | Input to fourth buffer of group 1; inverted output appears on 1Y4 when 1OE is low |
| 9 | 2Y1 | tri_state | Inverted output from second group bit 1; high-impedance state when 2OE is high |
| 10 | GND | power_in | Ground pin |
| 11 | 2A1 | input | Input to first buffer of group 2; inverted output appears on 2Y1 when 2OE is low |
| 12 | 1Y4 | tri_state | Inverted output from first group bit 4; high-impedance state when 1OE is high |
| 13 | 2A2 | input | Input to second buffer of group 2; inverted output appears on 2Y2 when 2OE is low |
| 14 | 1Y3 | tri_state | Inverted output from first group bit 3; high-impedance state when 1OE is high |
| 15 | 2A3 | input | Input to third buffer of group 2; inverted output appears on 2Y3 when 2OE is low |
| 16 | 1Y2 | tri_state | Inverted output from first group bit 2; high-impedance state when 1OE is high |
| 17 | 2A4 | input | Input to fourth buffer of group 2; inverted output appears on 2Y4 when 2OE is low |
| 18 | 1Y1 | tri_state | Inverted output from first group bit 1; high-impedance state when 1OE is high |
| 19 | 2OE | input | Output enable input for second group of buffers; active low to enable outputs, high places outputs in high-impedance state |
| 20 | VCC | power_in | Power supply pin; 2V to 5.5V operating range per section 5.3 |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Logic |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
SN74LV240APWR - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
sn74lv240apwr-etched.step/sn74lv240apwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lv240apwr.step/sn74lv240apwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (35 pp, sha256
f3a210b32d414ae6, retrieved 2026-09-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).