component

CD4067BMT

Public Made by Adom

by adom

HGSEMI Analog Switches, Multiplexers, TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterfacecd4067bmtfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

CD4067BMT

HGSEMI · Analog Switches, Multiplexers · TSSOP-24

CD4067BMT from HGSEMI, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Z bidirectional Common analog input/output that connects to whichever Yn is selected; analog signals can swing between VDD (positive limit) and VSS (negative limit), with VDD to VSS not to exceed 9V.
2 Y7 bidirectional Independent analog input/output switched to Z when selected by A0 to A3 with E LOW; analog swing is limited to VSS to VDD, and VDD to VSS may not exceed 9V.
3 Y6 bidirectional Independent analog input/output switched to Z when selected by A0 to A3 with E LOW; analog swing is limited to VSS to VDD, and VDD to VSS may not exceed 9V.
4 Y5 bidirectional Independent analog input/output switched to Z when selected by A0 to A3 with E LOW; analog swing is limited to VSS to VDD, and VDD to VSS may not exceed 9V.
5 Y4 bidirectional Independent analog input/output switched to Z when selected by A0 to A3 with E LOW; analog swing is limited to VSS to VDD, and VDD to VSS may not exceed 9V.
6 Y3 bidirectional Independent analog input/output switched to Z when selected by A0 to A3 with E LOW; analog swing is limited to VSS to VDD, and VDD to VSS may not exceed 9V.
7 Y2 bidirectional Independent analog input/output switched to Z when selected by A0 to A3 with E LOW; analog swing is limited to VSS to VDD, and VDD to VSS may not exceed 9V.
8 Y1 bidirectional Independent analog input/output switched to Z when selected by A0 to A3 with E LOW; analog swing is limited to VSS to VDD, and VDD to VSS may not exceed 9V.
9 Y0 bidirectional Independent analog input/output switched to Z when selected by A0 to A3 with E LOW; analog swing is limited to VSS to VDD, and VDD to VSS may not exceed 9V.
10 A0 input Address input (least significant bit) that selects one of the sixteen channels Y0 to Y15 when E is LOW; all switches are OFF when E is HIGH.
11 A1 input Address input that selects one of the sixteen channels Y0 to Y15 when E is LOW; all switches are OFF when E is HIGH.
12 VSS power_in Ground (0V) reference; all voltages in the datasheet are referenced to VSS, and VDD to VSS may not exceed 9V.
13 A3 input Address input (most significant bit) that selects one of the sixteen channels Y0 to Y15 when E is LOW; all switches are OFF when E is HIGH.
14 A2 input Address input that selects one of the sixteen channels Y0 to Y15 when E is LOW; all switches are OFF when E is HIGH.
15 E input Active LOW enable input (printed as E with an overline); when HIGH, all switches are in the high-impedance OFF-state independent of A0 to A3.
16 Y15 bidirectional Independent analog input/output switched to Z when selected by A0 to A3 with E LOW; analog swing is limited to VSS to VDD, and VDD to VSS may not exceed 9V.
17 Y14 bidirectional Independent analog input/output switched to Z when selected by A0 to A3 with E LOW; analog swing is limited to VSS to VDD, and VDD to VSS may not exceed 9V.
18 Y13 bidirectional Independent analog input/output switched to Z when selected by A0 to A3 with E LOW; analog swing is limited to VSS to VDD, and VDD to VSS may not exceed 9V.
19 Y12 bidirectional Independent analog input/output switched to Z when selected by A0 to A3 with E LOW; analog swing is limited to VSS to VDD, and VDD to VSS may not exceed 9V.
20 Y11 bidirectional Independent analog input/output switched to Z when selected by A0 to A3 with E LOW; analog swing is limited to VSS to VDD, and VDD to VSS may not exceed 9V.
21 Y10 bidirectional Independent analog input/output switched to Z when selected by A0 to A3 with E LOW; analog swing is limited to VSS to VDD, and VDD to VSS may not exceed 9V.
22 Y9 bidirectional Independent analog input/output switched to Z when selected by A0 to A3 with E LOW; analog swing is limited to VSS to VDD, and VDD to VSS may not exceed 9V.
23 Y8 bidirectional Independent analog input/output switched to Z when selected by A0 to A3 with E LOW; analog swing is limited to VSS to VDD, and VDD to VSS may not exceed 9V.
24 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer HGSEMI
Package TSSOP-24
Category Interface
Pins 24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VDD -0.5 12 V 6
input clamping current IIK -10 10 mA VI<0.5V or VI>VDD+0.5V 6
switch current I -10 10 mA 6
input voltage VI -0.5 V all inputs 6
storage temperature Tstg -65 150 °C 6
total power dissipation Ptot 500 mW 6
supply voltage VDD 3 5 9 V 6
ambient temperature Tamb -40 105 °C in free air 6
input voltage VI 0 V 6
multiplexer switch input current capability 25 mA 6
output load resistance 100 Ω 6
LOW-level input voltage VIL 1.5 V /IO/<1uA; VDD=5V, VO=0.5V or 4.5V 7
LOW-level input voltage VIL 3 V /IO/<1uA; VDD=9V, VO=1.0V or 9V 7
HIGH-level input voltage VIH 3.5 V /IO/<1uA; VDD=5V, VO=0.5V or 4.5V 7
HIGH-level input voltage VIH 7 V /IO/<1uA; VDD=9V, VO=1.0V or 9V 7
input leakage current II -5 0.1 10 uA VI=0V or 9V, VDD=9V 7
OFF-state leakage current IS(OFF) -100 0.1 100 nA VSS=0V; VDD=9V 7
supply current IDD 0.04 5 uA all valid input combinations; IO=0A; VDD=5V 7
supply current IDD 0.04 10 uA all valid input combinations; IO=0A; VDD=9V 7
input capacitance CI 5 7.5 pF any address or inhibit input 7
ON resistance RON 470 1050 Ω VSS≤Vis≤VDD; VDD=5V 7
ON resistance RON 180 400 Ω VSS≤Vis≤VDD; VDD=9V 7
LOW-level input voltage VIL 1.5 V Tamb=-40℃; /IO/<1uA; VDD=5V, VO=0.5V or 4.5V 8
LOW-level input voltage VIL 3 V Tamb=-40℃; /IO/<1uA; VDD=9V, VO=1.0V or 9V 8
HIGH-level input voltage VIH 3.5 V Tamb=-40℃; /IO/<1uA; VDD=5V, VO=0.5V or 4.5V 8
HIGH-level input voltage VIH 7 V Tamb=-40℃; /IO/<1uA; VDD=9V, VO=1.0V or 9V 8
input leakage current II -0.1 0.1 uA Tamb=-40℃; VI=0V or 9V, VDD=9V 8
input leakage current II -1 1 uA Tamb=+85℃; VI=0V or 9V, VDD=9V 8
OFF-state leakage current IS(OFF) -100 100 nA Tamb=-40℃; VSS=0V; VDD=9V 8
OFF-state leakage current IS(OFF) -1000 1000 nA Tamb=+85℃; VSS=0V; VDD=9V 8
supply current IDD 5 uA Tamb=-40℃; all valid input combinations; IO=0A; VDD=5V 8
supply current IDD 150 uA Tamb=+85℃; all valid input combinations; IO=0A; VDD=5V 8
supply current IDD 10 uA Tamb=-40℃; all valid input combinations; IO=0A; VDD=9V 8
supply current IDD 300 uA Tamb=+85℃; all valid input combinations; IO=0A; VDD=9V 8
ON resistance RON 850 Ω Tamb=-40℃; VSS≤Vis≤VDD; VDD=5V 8
ON resistance RON 1200 Ω Tamb=+85℃; VSS≤Vis≤VDD; VDD=5V 8
ON resistance RON 1300 Ω Tamb=+105℃; VSS≤Vis≤VDD; VDD=5V 8
ON resistance RON 330 Ω Tamb=-40℃; VSS≤Vis≤VDD; VDD=9V 8
ON resistance RON 520 Ω Tamb=+85℃; VSS≤Vis≤VDD; VDD=9V 8
ON resistance RON 550 Ω Tamb=+105℃; VSS≤Vis≤VDD; VDD=9V 8
HIGH to LOW propagation delay time tPHL 30 60 ns Yn, Z to Z, Yn; see Figure 5; VDD=5V 9
HIGH to LOW propagation delay time tPHL 15 30 ns Yn, Z to Z, Yn; see Figure 5; VDD=9V 9
LOW to HIGH propagation delay time tPLH 30 60 ns Yn, Z to Z, Yn; see Figure 5; VDD=5V 9
LOW to HIGH propagation delay time tPLH 15 30 ns Yn, Z to Z, Yn; see Figure 5; VDD=9V 9
HIGH to OFF-state propagation delay time tPHZ 325 650 ns E to Yn, Z; see Figure 7; VDD=5V 9
HIGH to OFF-state propagation delay time tPHZ 135 270 ns E to Yn, Z; see Figure 7; VDD=9V 9
LOW to OFF-state propagation delay time tPLZ 325 650 ns E to Yn, Z; see Figure 7; VDD=5V 9
LOW to OFF-state propagation delay time tPLZ 135 270 ns E to Yn, Z; see Figure 7; VDD=9V 9

CAD (KiCad official)

  • Symbol: CD4067BMT
  • Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
  • 3D model: TSSOP-24 (KiCad packages3D, STEP)
  • 3D model files: cd4067bmt-etched.step / cd4067bmt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4067bmt.step / cd4067bmt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (16 pp, sha256 aa8ede1d76a4d45a, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF