component
SN74LVT125PWR
Public Made by Adomby adom
Texas Instruments Buffers, Drivers, Receivers, Transceivers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads on click. Unloads only if this page sits in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads on click. Unloads only if this page sits in the background.
PCB Footprint
Open full view ↗Loads on click. Unloads only if this page sits in the background.
Datasheet
Open in new tab ↗Loads on click. Unloads only if this page sits in the background.
README
markdownSN74LVT125PWR
Texas Instruments · Buffers, Drivers, Receivers, Transceivers · TSSOP-14
SN74LVT125PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OE | input | Output-enable input for buffer 1; when high, 1Y is forced to the high-impedance state, and when low, 1Y follows 1A. |
| 2 | 1A | input | Data input for buffer 1, whose logic level is passed to output 1Y when 1OE is low. |
| 3 | 1Y | tri_state | 3-state buffer output 1; drives the logic level of 1A when 1OE is low and goes to a high-impedance state when 1OE is high. |
| 4 | 2OE | input | Output-enable input for buffer 2; when high, 2Y is forced to the high-impedance state, and when low, 2Y follows 2A. |
| 5 | 2A | input | Data input for buffer 2, whose logic level is passed to output 2Y when 2OE is low. |
| 6 | 2Y | tri_state | 3-state buffer output 2; drives the logic level of 2A when 2OE is low and goes to a high-impedance state when 2OE is high. |
| 7 | GND | power_in | Ground supply pin for the device. |
| 8 | 3Y | tri_state | 3-state buffer output 3; drives the logic level of 3A when 3OE is low and goes to a high-impedance state when 3OE is high. |
| 9 | 3A | input | Data input for buffer 3, whose logic level is passed to output 3Y when 3OE is low. |
| 10 | 3OE | input | Output-enable input for buffer 3; when high, 3Y is forced to the high-impedance state, and when low, 3Y follows 3A. |
| 11 | 4Y | tri_state | 3-state buffer output 4; drives the logic level of 4A when 4OE is low and goes to a high-impedance state when 4OE is high. |
| 12 | 4A | input | Data input for buffer 4, whose logic level is passed to output 4Y when 4OE is low. |
| 13 | 4OE | input | Output-enable input for buffer 4; when high, 4Y is forced to the high-impedance state, and when low, 4Y follows 4A. |
| 14 | VCC | power_in | Positive supply voltage pin, recommended operating range 2.7 V to 3.6 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
SN74LVT125PWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
sn74lvt125pwr-etched.step/sn74lvt125pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);sn74lvt125pwr.step/sn74lvt125pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
55cb78c6c938d1ab, retrieved 2026-09-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).