component
CD74HC107M
Public Made by Adomby adom
Texas Instruments Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD74HC107M
Texas Instruments · Flip Flops · SOIC-14
CD74HC107M from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1J | input | J synchronous data input of flip-flop 1, sampled on the negative-going edge of 1CP with the setup and hold times given in the switching specifications. |
| 2 | 1Q̄ | output | Complementary output of flip-flop 1 (inverse of 1Q); standard outputs are specified for 10 LSTTL loads. |
| 3 | 1Q | output | True output of flip-flop 1; standard outputs are specified for 10 LSTTL loads over the temperature range. |
| 4 | 1K | input | K synchronous data input of flip-flop 1, sampled on the negative-going edge of 1CP with the setup and hold times given in the switching specifications. |
| 5 | 2Q | output | True output of flip-flop 2; standard outputs are specified for 10 LSTTL loads over the temperature range. |
| 6 | 2Q̄ | output | Complementary output of flip-flop 2 (inverse of 2Q); standard outputs are specified for 10 LSTTL loads. |
| 7 | GND | power_in | Ground return for the device; input and output voltages are specified from 0V to VCC relative to this pin. |
| 8 | 2J | input | J synchronous data input of flip-flop 2, sampled on the negative-going edge of 2CP with the setup and hold times given in the switching specifications. |
| 9 | 2CP | input | Negative-edge triggered clock input for flip-flop 2, with hysteresis for improved noise immunity. |
| 10 | 2R | input | Asynchronous active-low reset input for flip-flop 2, accomplished by a low-level input. |
| 11 | 2K | input | K synchronous data input of flip-flop 2, sampled on the negative-going edge of 2CP with the setup and hold times given in the switching specifications. |
| 12 | 1CP | input | Negative-edge triggered clock input for flip-flop 1, with hysteresis for improved noise immunity. |
| 13 | 1R | input | Asynchronous active-low reset input for flip-flop 1, accomplished by a low-level input. |
| 14 | VCC | power_in | Positive supply: 2V to 6V for HC types and 4.5V to 5.5V for HCT types. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
CD74HC107M - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
cd74hc107m-etched.step/cd74hc107m-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd74hc107m.step/cd74hc107m.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (20 pp, sha256
43434ff57a9d1718, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).