component
TPS77633DR
Public Made by Adomby adom
Texas Instruments Linear Voltage Regulators (LDO), SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTPS77633DR
Texas Instruments · Linear Voltage Regulators (LDO) · SOIC-8
TPS77633DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference pin for the regulator. |
| 2 | EN | input | Negative-polarity enable input; applying a TTL high signal to EN shuts the regulator down, reducing quiescent current to 1µA at TJ = +25°C, and EN should be tied to ground if the shutdown feature is not used. Absolute maximum voltage at EN is −0.3 V to +16.5 V. |
| 3 | IN | power_in | Input voltage pin; absolute maximum input voltage range is −0.3 V to +13.5 V. |
| 4 | IN | power_in | Input voltage pin (second IN pin, connected in parallel with pin 3); absolute maximum input voltage range is −0.3 V to +13.5 V. |
| 5 | OUT | power_out | Regulated output voltage; an output capacitor of at least 10µF with ESR between 50mΩ and 1.5Ω is required between OUT and GND for stability. |
| 6 | OUT | power_out | Regulated output voltage (second OUT pin, connected in parallel with pin 5); an output capacitor of at least 10µF with ESR between 50mΩ and 1.5Ω is required between OUT and GND for stability. |
| 7 | FB/NC | passive | Feedback voltage input for the adjustable version only; on the fixed-voltage version this pin is not internally connected (NC). |
| 8 | RESET/PG | output | Open-drain power-good (PG) output of the TPS776xx family, which the TPS77633 belongs to; it requires an external pullup resistor, may be left floating if unused, and has a maximum voltage of 16.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage range | VIN | 2.7 | 10 | V | 3 | ||
| Output voltage accuracy | VOUT | -2 | 2 | % | 10µA < IOUT < 500mA | 3 | |
| Dropout voltage (TPS77633) | VDO | 169 | 287 | mV | IOUT = 500mA | 3 | |
| Output current limit | ICL | 1.2 | 1.6 | 1.9 | A | VOUT = 0V | 3 |
| Operating junction temperature range | TJ | -40 | 125 | °C | 3 | ||
| High-level enable input voltage | VEN(HI) | 1.7 | V | 3 | |||
| Low-level enable input voltage | VEN(LO) | 0.9 | V | 3 | |||
| Input current (EN) | -1 | 0 | 1 | µA | EN = 0V | 3 | |
| Input current (EN) | -1 | 1 | µA | EN = VIN | 3 | ||
| Standby current | ISTBY | 1 | µA | EN = VIN, at TJ = +25°C, 2.7V < VIN < 10V | 3 | ||
| Standby current | ISTBY | 10 | µA | EN = VIN, 2.7V < VIN < 10V | 3 | ||
| Minimum input voltage for valid PG | 1.1 | V | IOUT(PG) = 300µA | 3 | |||
| PG trip threshold voltage | 92 | 98 | %VOUT | VOUT decreasing | 3 | ||
| PG output low voltage | 0.15 | 0.4 | V | VIN = 2.7V, IOUT(PG) = 1mA | 3 | ||
| PG leakage current | 1 | µA | V(PG) = 5V | 3 | |||
| Input voltage range VIN | VIN | -0.3 | 13.5 | V | Over operating temperature range (unless otherwise noted); with respect to network ground | 2 | |
| Voltage range at EN | -0.3 | 16.5 | V | 2 | |||
| Maximum PG voltage (TPS776xx) | 16.5 | V | 2 | ||||
| Voltage range at OUT, FB | 7 | V | 2 | ||||
| Storage junction temperature range | TSTG | -65 | 150 | °C | 2 | ||
| ESD rating, HBM | 2 | kV | HBM | 2 | |||
| Power dissipation, D package, 0 CFM | 568 | mW | TA < +25°C, board D, airflow 0 CFM | 2 | |||
| Power dissipation, D package, 0 CFM | 312 | mW | TA = +70°C, board D, airflow 0 CFM | 2 | |||
| Power dissipation, D package, 0 CFM | 227 | mW | TA = +85°C, board D, airflow 0 CFM | 2 | |||
| Power dissipation, D package, 250 CFM | 904 | mW | TA < +25°C, board D, airflow 250 CFM | 2 | |||
| Power dissipation, D package, 250 CFM | 497 | mW | TA = +70°C, board D, airflow 250 CFM | 2 | |||
| Power dissipation, D package, 250 CFM | 362 | mW | TA = +85°C, board D, airflow 250 CFM | 2 | |||
| Derating factor above TA = +25°C, D package, 0 CFM | 5.68 | mW/°C | board D, airflow 0 CFM | 2 | |||
| Derating factor above TA = +25°C, D package, 250 CFM | 9.04 | mW/°C | board D, airflow 250 CFM | 2 |
CAD (KiCad official)
- Symbol:
TPS77633DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tps77633dr-etched.step/tps77633dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tps77633dr.step/tps77633dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (31 pp, sha256
7764c2df7df2d85f, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).